forked from M-Labs/artiq-zynq
cxp upconn: rename modules & cleanup
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d88af397ec
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98bb49e1b5
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@ -89,7 +89,7 @@ class SERDES_10bits(Module):
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)
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)
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]
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]
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class Transmission_Scheduler(Module):
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class Packets_Scheduler(Module):
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def __init__(self, tx_fifos):
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def __init__(self, tx_fifos):
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self.tx_enable = Signal()
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self.tx_enable = Signal()
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@ -203,9 +203,7 @@ class TxFIFOs(Module):
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self.sink_full[i].eq(fifo.sink.ack),
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self.sink_full[i].eq(fifo.sink.ack),
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fifo.sink.data.eq(self.sink_data[i]),
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fifo.sink.data.eq(self.sink_data[i]),
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fifo.sink.k.eq(self.sink_k[i]),
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fifo.sink.k.eq(self.sink_k[i]),
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]
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self.sync += [
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If(self.source_ack[i],
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If(self.source_ack[i],
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# reset ack after asserted
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# reset ack after asserted
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self.source_ack[i].eq(0),
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self.source_ack[i].eq(0),
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@ -233,7 +231,7 @@ class CXP_UpConn(Module):
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self.submodules.cg = cg = UpConn_ClockGen(sys_clk_freq)
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self.submodules.cg = cg = UpConn_ClockGen(sys_clk_freq)
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self.submodules.tx_fifos = tx_fifos = TxFIFOs(nfifos, fifo_depth)
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self.submodules.tx_fifos = tx_fifos = TxFIFOs(nfifos, fifo_depth)
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self.submodules.scheduler = scheduler = CEInserter()(Transmission_Scheduler(tx_fifos))
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self.submodules.scheduler = scheduler = CEInserter()(Packets_Scheduler(tx_fifos))
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self.submodules.serdes = serdes = CEInserter()(SERDES_10bits(pad))
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self.submodules.serdes = serdes = CEInserter()(SERDES_10bits(pad))
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self.comb += [
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self.comb += [
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