diff --git a/src/gateware/cxp_upconn.py b/src/gateware/cxp_upconn.py
index ba1ecad..2292845 100644
--- a/src/gateware/cxp_upconn.py
+++ b/src/gateware/cxp_upconn.py
@@ -89,7 +89,7 @@ class SERDES_10bits(Module):
             )
         ]
 
-class Transmission_Scheduler(Module):
+class Packets_Scheduler(Module):
     def __init__(self, tx_fifos):
         self.tx_enable = Signal()
 
@@ -203,9 +203,7 @@ class TxFIFOs(Module):
                 self.sink_full[i].eq(fifo.sink.ack),
                 fifo.sink.data.eq(self.sink_data[i]),
                 fifo.sink.k.eq(self.sink_k[i]),
-            ]
 
-            self.sync += [
                 If(self.source_ack[i], 
                     # reset ack after asserted 
                     self.source_ack[i].eq(0),
@@ -233,7 +231,7 @@ class CXP_UpConn(Module):
         self.submodules.cg = cg = UpConn_ClockGen(sys_clk_freq)
         self.submodules.tx_fifos = tx_fifos = TxFIFOs(nfifos, fifo_depth)
 
-        self.submodules.scheduler = scheduler = CEInserter()(Transmission_Scheduler(tx_fifos))
+        self.submodules.scheduler = scheduler = CEInserter()(Packets_Scheduler(tx_fifos))
         self.submodules.serdes = serdes = CEInserter()(SERDES_10bits(pad))
 
         self.comb += [