forked from M-Labs/artiq-zynq
cxp GW: add debug pipeline for downconn
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@ -30,8 +30,11 @@ class DownConn_Interface(Module, AutoCSR):
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self.submodules.conv = conv = stream.StrideConverter(upconn_layout, downconn_layout, reverse=True)
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self.submodules.debug_out = debug_out = RX_Debug_Buffer()
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rx_pipeline = [debug_src, conv, debug_out]
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tx_pipeline = [debug_src, conv, phy.sinks[0]]
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for s, d in zip(tx_pipeline, tx_pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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rx_pipeline = [phy.sources[0], debug_out]
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for s, d in zip(rx_pipeline, rx_pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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