diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py
index e33b0d7..00a9755 100755
--- a/src/gateware/zc706.py
+++ b/src/gateware/zc706.py
@@ -698,10 +698,13 @@ class CXP_FMC():
         self.csr_devices.append("cxp")
 
         # max freq of cxp_gtx_rx = linerate/internal_datawidth = 12.5Gbps/40 = 312.5MHz
-        # 4.0 works on all CXP linerate, 3.2 has some strange setup/hold time problem even on 12.5Gbps
-        platform.add_period_constraint(self.cxp.downconn.gtx.cd_cxp_gtx_tx.clk, 4.0)
-        platform.add_period_constraint(self.cxp.downconn.gtx.cd_cxp_gtx_rx.clk, 4.0)
-        platform.add_false_path_constraints(self.cxp.downconn.gtx.cd_cxp_gtx_tx.clk, self.cxp.downconn.gtx.cd_cxp_gtx_rx.clk)
+        # zc706 use speed grade 2 which only support up to 10.3125Gbps (4ns)
+        # pushing to 12.5Gbps (3.2ns) will result in Pulse width violation but setup/hold times are met
+        for gtx in self.cxp.downconn.gtxs:
+            platform.add_period_constraint(gtx.cd_cxp_gtx_tx.clk, 3.2)
+            platform.add_period_constraint(gtx.cd_cxp_gtx_rx.clk, 3.2)
+            # constraint the CLK path 
+            platform.add_false_path_constraints(self.sys_crg.cd_sys.clk, gtx.cd_cxp_gtx_tx.clk, gtx.cd_cxp_gtx_rx.clk)
 
         rtio_channels = []
         # FIXME remove this placeholder RTIO channel