diff --git a/src/gateware/cxp.py b/src/gateware/cxp.py
index 5e67a98..aace844 100644
--- a/src/gateware/cxp.py
+++ b/src/gateware/cxp.py
@@ -28,9 +28,13 @@ class CXP_PHYS(Module, AutoCSR):
         
 
 class CXP_Core(Module, AutoCSR):
-    def __init__(self, phy):
-        self.submodules.tx = TX_Pipeline(phy.tx)
-        self.submodules.rx = RX_Pipeline(phy.rx)
+    def __init__(self, phy, ctrl_buffer_depth=32, nrxslot=4):
+        # control buffer is only 32 words (128 bytes) for compatibility with version1.x compliant Devices
+        # Section 12.1.6 (CXP-001-2021)
+        self.buffer_depth, self.nslots = ctrl_buffer_depth, nrxslot
+        
+        self.submodules.tx = TX_Pipeline(phy.tx, ctrl_buffer_depth)
+        self.submodules.rx = RX_Pipeline(phy.rx, ctrl_buffer_depth, nrxslot)
 
     def get_tx_port(self):
         return self.tx.writer.mem.get_port(write_capable=True)
@@ -45,7 +49,7 @@ class CXP_Core(Module, AutoCSR):
         # return self.downconn.bootstrap.mem.depth*self.downconn.bootstrap.mem.width // 8 # 0x2000
 
     def get_mem_size(self):
-        return word_width * buffer_count * buffer_depth // 8
+        return word_width * self.buffer_depth * self.nslots // 8
 
     def get_rx_port(self):
         return self.rx.reader.mem.get_port(write_capable=False)
@@ -55,7 +59,7 @@ class CXP_Core(Module, AutoCSR):
         return self.rx.reader.mem.depth*self.downconn.bootstrap.mem.width // 8
 
 class RX_Pipeline(Module, AutoCSR):
-    def __init__(self, phy):
+    def __init__(self, phy, ctrl_buffer_depth, nslot):
         self.ready = CSRStatus()
 
         # # #
@@ -124,7 +128,7 @@ class RX_Pipeline(Module, AutoCSR):
         ]
 
         # Priority level 2 packet - data, test packet
-        self.submodules.reader = reader = cdr(Control_Packet_Reader())
+        self.submodules.reader = reader = cdr(Control_Packet_Reader(ctrl_buffer_depth, nslot))
 
         self.reader_decode_err = CSR()
         self.reader_buffer_err = CSR()
@@ -175,7 +179,7 @@ class RX_Pipeline(Module, AutoCSR):
         # reader cicular memory control interface
         self.packet_type = CSRStatus(8)
         self.pending_packet = CSR()
-        self.read_ptr = CSRStatus(log2_int(buffer_count))
+        self.read_ptr = CSRStatus(log2_int(nslot))
 
         self.specials += [
             MultiReg(reader.packet_type, self.packet_type.status),
@@ -211,7 +215,7 @@ class RX_Pipeline(Module, AutoCSR):
 
         
 class TX_Pipeline(Module, AutoCSR):
-    def __init__(self, phy):
+    def __init__(self, phy, ctrl_buffer_depth):
         # Transmission Pipeline
         #
         #              32                                                  32           8
@@ -240,10 +244,10 @@ class TX_Pipeline(Module, AutoCSR):
 
         # 2: All other packets (data & test packet)
         # Control is not timing dependent, all the data packets are handled in firmware
-        self.submodules.writer = writer = Control_Packet_Writer()
+        self.submodules.writer = writer = Control_Packet_Writer(ctrl_buffer_depth)
 
         # writer memory control interface
-        self.writer_word_len = CSRStorage(log2_int(buffer_depth))
+        self.writer_word_len = CSRStorage(log2_int(ctrl_buffer_depth))
         self.writer_stb = CSR()
         self.writer_stb_testseq = CSR()
         self.writer_busy = CSRStatus()