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zc706 GW: reorder cxp rx mem to fix tx read issue

This commit is contained in:
morgan 2024-10-14 17:13:18 +08:00
parent 30cc069a29
commit 9379503297
1 changed files with 6 additions and 8 deletions
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14
src/gateware/zc706.py
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@ -718,19 +718,17 @@ class CXP_FMC():
self.csr_devices.append(cxp_name) self.csr_devices.append(cxp_name)
cxp_csr_group.append(cxp_name) cxp_csr_group.append(cxp_name)
rx_mem_name = "cxp_rx" + str(i) + "_mem"
rx_mem_size = cxp_interface.get_rx_mem_size()
cxp_rx_mem_group.append(rx_mem_name)
memory_address = self.axi2csr.register_port(cxp_interface.get_rx_port(), rx_mem_size)
self.add_memory_region(rx_mem_name, self.mem_map["csr"] + memory_address, rx_mem_size)
tx_mem_name = "cxp_tx" + str(i) + "_mem" tx_mem_name = "cxp_tx" + str(i) + "_mem"
tx_mem_size = cxp_interface.get_tx_mem_size() tx_mem_size = cxp_interface.get_tx_mem_size()
cxp_tx_mem_group.append(tx_mem_name)
memory_address = self.axi2csr.register_port(cxp_interface.get_tx_port(), tx_mem_size) memory_address = self.axi2csr.register_port(cxp_interface.get_tx_port(), tx_mem_size)
self.add_memory_region(tx_mem_name, self.mem_map["csr"] + memory_address, tx_mem_size) self.add_memory_region(tx_mem_name, self.mem_map["csr"] + memory_address, tx_mem_size)
cxp_tx_mem_group.append(tx_mem_name)
rx_mem_name = "cxp_rx" + str(i) + "_mem"
rx_mem_size = cxp_interface.get_rx_mem_size()
memory_address = self.axi2csr.register_port(cxp_interface.get_rx_port(), rx_mem_size)
self.add_memory_region(rx_mem_name, self.mem_map["csr"] + memory_address, rx_mem_size)
cxp_rx_mem_group.append(rx_mem_name)
# DEBUG loopback tx memory # DEBUG loopback tx memory
loopback_mem_name = "cxp_loopback_tx" + str(i) + "_mem" loopback_mem_name = "cxp_loopback_tx" + str(i) + "_mem"