forked from M-Labs/artiq-zynq
downconn FW: add trig ack testing
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610b53e7f7
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925237face
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@ -37,27 +37,33 @@ pub fn loopback_testing(timer: &mut GlobalTimer, speed: CXP_SPEED) {
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while csr::cxp::downconn_phy_rx_ready_read() != 1 {}
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info!("rx ready!");
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cxp_proto::downconn_debug_send_trig_ack();
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cxp_proto::downconn_debug_send(&cxp_proto::Packet::CtrlRead {
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addr: 0x00,
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length: 0x04,
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});
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timer.delay_us(200); // wait packet has arrive at async fifo in
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unsafe {
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csr::cxp::downconn_phy_tx_stb_write(1);
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timer.delay_us(200);
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csr::cxp::downconn_phy_tx_stb_write(0);
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}
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info!("trig ack = {}", csr::cxp::downconn_trig_ack_read());
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csr::cxp::downconn_trig_clr_write(1);
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info!("after clr trig ack = {}", csr::cxp::downconn_trig_ack_read());
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// TODO: investigate how to make my packet appear
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// TODO: discard idle word
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// DEBUG: print loopback packets
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const LEN: usize = 20;
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let mut pak_arr: [u32; LEN] = [0; LEN];
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let mut k_arr: [u8; LEN] = [0; LEN];
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let mut i: usize = 0;
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unsafe {
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while csr::cxp::downconn_debug_out_dout_valid_read() == 1 {
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pak_arr[i] = csr::cxp::downconn_debug_out_dout_pak_read();
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k_arr[i] = csr::cxp::downconn_debug_out_kout_pak_read();
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// println!("received {:#04X}", pak_arr[i]);
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csr::cxp::downconn_debug_out_inc_write(1);
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i += 1;
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@ -65,8 +71,7 @@ pub fn loopback_testing(timer: &mut GlobalTimer, speed: CXP_SPEED) {
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break;
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}
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}
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}
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cxp_proto::print_packetu32(&pak_arr)
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cxp_proto::print_packetu32(&pak_arr, &k_arr);
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}
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}
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