diff --git a/src/libboard_artiq/src/cxp_downconn.rs b/src/libboard_artiq/src/cxp_downconn.rs index e8211b7..5b2bf59 100644 --- a/src/libboard_artiq/src/cxp_downconn.rs +++ b/src/libboard_artiq/src/cxp_downconn.rs @@ -37,36 +37,41 @@ pub fn loopback_testing(timer: &mut GlobalTimer, speed: CXP_SPEED) { while csr::cxp::downconn_phy_rx_ready_read() != 1 {} info!("rx ready!"); + cxp_proto::downconn_debug_send_trig_ack(); + cxp_proto::downconn_debug_send(&cxp_proto::Packet::CtrlRead { addr: 0x00, length: 0x04, }); timer.delay_us(200); // wait packet has arrive at async fifo in - unsafe { - csr::cxp::downconn_phy_tx_stb_write(1); - timer.delay_us(200); - csr::cxp::downconn_phy_tx_stb_write(0); - } + csr::cxp::downconn_phy_tx_stb_write(1); + timer.delay_us(200); + csr::cxp::downconn_phy_tx_stb_write(0); + + info!("trig ack = {}", csr::cxp::downconn_trig_ack_read()); + csr::cxp::downconn_trig_clr_write(1); + info!("after clr trig ack = {}", csr::cxp::downconn_trig_ack_read()); // TODO: investigate how to make my packet appear // TODO: discard idle word + // DEBUG: print loopback packets const LEN: usize = 20; let mut pak_arr: [u32; LEN] = [0; LEN]; + let mut k_arr: [u8; LEN] = [0; LEN]; let mut i: usize = 0; - unsafe { - while csr::cxp::downconn_debug_out_dout_valid_read() == 1 { - pak_arr[i] = csr::cxp::downconn_debug_out_dout_pak_read(); - // println!("received {:#04X}", pak_arr[i]); - csr::cxp::downconn_debug_out_inc_write(1); - i += 1; - if i == LEN { - break; - } + while csr::cxp::downconn_debug_out_dout_valid_read() == 1 { + pak_arr[i] = csr::cxp::downconn_debug_out_dout_pak_read(); + k_arr[i] = csr::cxp::downconn_debug_out_kout_pak_read(); + // println!("received {:#04X}", pak_arr[i]); + csr::cxp::downconn_debug_out_inc_write(1); + i += 1; + if i == LEN { + break; } } - cxp_proto::print_packetu32(&pak_arr) + cxp_proto::print_packetu32(&pak_arr, &k_arr); } }