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cxp GW: add test packet & fix endian for downconn

This commit is contained in:
morgan 2024-09-24 10:10:54 +08:00
parent ef0ab1f526
commit 9178ca4576
1 changed files with 25 additions and 3 deletions
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28
src/gateware/cxp.py
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@ -26,16 +26,18 @@ class DownConn_Interface(Module, AutoCSR):
# DEBUG: TX pipeline # DEBUG: TX pipeline
self.submodules.debug_src = debug_src = TX_Command_Packet() self.submodules.debug_src = debug_src = TX_Command_Packet()
self.submodules.trig_ack = trig_ack = Trigger_ACK() self.submodules.trig_ack = trig_ack = Trigger_ACK()
self.submodules.mux = mux = stream.Multiplexer(upconn_layout, 2) self.submodules.testseq = testseq = TX_Test_Packet()
self.submodules.conv = conv = stream.StrideConverter(upconn_layout, downconn_layout, reverse=True) self.submodules.mux = mux = stream.Multiplexer(upconn_layout, 3)
self.submodules.conv = conv = stream.StrideConverter(upconn_layout, downconn_layout)
self.ack = CSR() self.ack = CSR()
self.mux_sel = CSRStorage() self.mux_sel = CSRStorage(4)
self.sync += trig_ack.ack.eq(self.ack.re), self.sync += trig_ack.ack.eq(self.ack.re),
self.comb += [ self.comb += [
debug_src.source.connect(mux.sink0), debug_src.source.connect(mux.sink0),
trig_ack.source.connect(mux.sink1), trig_ack.source.connect(mux.sink1),
testseq.source.connect(mux.sink2),
mux.sel.eq(self.mux_sel.storage) mux.sel.eq(self.mux_sel.storage)
] ]
@ -54,9 +56,11 @@ class DownConn_Interface(Module, AutoCSR):
self.packet_type = CSRStatus(8) self.packet_type = CSRStatus(8)
self.decoder_error = CSRStatus() self.decoder_error = CSRStatus()
self.test_error = CSRStatus()
self.comb += [ self.comb += [
self.packet_type.status.eq(recv_path.packet_type), self.packet_type.status.eq(recv_path.packet_type),
self.decoder_error.status.eq(recv_path.decoder_err), self.decoder_error.status.eq(recv_path.decoder_err),
self.test_error.status.eq(recv_path.test_err),
] ]
# DEBUG: CSR # DEBUG: CSR
@ -67,6 +71,24 @@ class DownConn_Interface(Module, AutoCSR):
recv_path.trig_clr.eq(self.trig_clr.re), recv_path.trig_clr.eq(self.trig_clr.re),
] ]
pak_start = Signal()
self.sync += [
pak_start.eq(recv_path.packet_decoder.sink.data == 0xFBFBFBFB),
]
self.specials += [
# # pmod 0-7 pin
Instance("OBUF", i_I=recv_path.packet_decoder.test_err, o_O=pmod_pads[0]),
Instance("OBUF", i_I=pak_start, o_O=pmod_pads[1]),
# Instance("OBUF", i_I=fifo_in.source.ack, o_O=pmod_pads[2]),
# Instance("OBUF", i_I=gtx.comma_checker.aligner_en, o_O=pmod_pads[3]),
# Instance("OBUF", i_I=gtx.comma_checker.check_reset, o_O=pmod_pads[4]),
# Instance("OBUF", i_I=gtx.comma_checker.has_comma, o_O=pmod_pads[5]),
# Instance("OBUF", i_I=gtx.comma_checker.has_error, o_O=pmod_pads[6]),
# Instance("OBUF", i_I=gtx.comma_checker.ready_sys, o_O=pmod_pads[7]),
]
class UpConn_Interface(Module, AutoCSR): class UpConn_Interface(Module, AutoCSR):
def __init__(self, upconn_pads, sys_clk_freq, debug_sma, pmod_pads): def __init__(self, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):