forked from M-Labs/artiq-zynq
use new core1 startup mechanism
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parent
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commit
90faeb6fa2
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@ -15,7 +15,7 @@ in
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version = "0.1.0";
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src = ./src;
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cargoSha256 = "1b40w3ycc0hx6hahxgz935vv01q1lirbrn4cb4k0r3dmgzvsdk6l";
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cargoSha256 = "0pa5m7pwpiyd1agfgfhywd8dkm6pbjx76nca4dngpw77h893c5bc";
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nativeBuildInputs = [
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pkgs.gnumake
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@ -153,7 +153,7 @@ dependencies = [
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[[package]]
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name = "libasync"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#ce844f1b026b15f77432de0e24942ff220add283"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#4e1f46b3e232609b7bc8d818f60ce07fa769d93b"
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dependencies = [
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"embedded-hal",
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"libcortex_a9",
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@ -165,7 +165,7 @@ dependencies = [
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[[package]]
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name = "libboard_zynq"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#ce844f1b026b15f77432de0e24942ff220add283"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#4e1f46b3e232609b7bc8d818f60ce07fa769d93b"
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dependencies = [
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"bit_field",
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"embedded-hal",
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@ -181,7 +181,7 @@ dependencies = [
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[[package]]
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name = "libcortex_a9"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#ce844f1b026b15f77432de0e24942ff220add283"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#4e1f46b3e232609b7bc8d818f60ce07fa769d93b"
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dependencies = [
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"bit_field",
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"libregister",
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@ -190,7 +190,7 @@ dependencies = [
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[[package]]
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name = "libregister"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#ce844f1b026b15f77432de0e24942ff220add283"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#4e1f46b3e232609b7bc8d818f60ce07fa769d93b"
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dependencies = [
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"bit_field",
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"vcell",
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@ -200,7 +200,7 @@ dependencies = [
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[[package]]
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name = "libsupport_zynq"
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version = "0.0.0"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#ce844f1b026b15f77432de0e24942ff220add283"
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source = "git+https://git.m-labs.hk/M-Labs/zc706.git#4e1f46b3e232609b7bc8d818f60ce07fa769d93b"
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dependencies = [
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"compiler_builtins",
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"libboard_zynq",
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@ -28,7 +28,7 @@ pub struct Control {
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impl Control {
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pub fn start() -> Self {
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let core1 = Core1::start();
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let core1 = Core1::start(true);
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let (core0_tx, core1_rx) = sync_channel(4);
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let (core1_tx, core0_rx) = sync_channel(4);
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@ -12,7 +12,7 @@ use libboard_zynq::{
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logger,
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timer::GlobalTimer,
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};
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use libsupport_zynq::boot;
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use libsupport_zynq as _;
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extern "C" {
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@ -48,7 +48,7 @@ pub fn main_core0() {
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if result < 0 {
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error!("decompression failed");
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} else {
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boot::Core1::start();
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// Start core0 only, for compatibility with FSBL.
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info!("executing payload");
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unsafe {
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(mem::transmute::<*mut u8, fn()>(ddr.ptr::<u8>()))();
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@ -60,7 +60,5 @@ pub fn main_core0() {
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#[no_mangle]
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pub fn main_core1() {
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unsafe {
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(mem::transmute::<u32, fn()>(0x00100000))();
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}
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panic!("core1 started but should not have");
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}
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