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downconn GW: update docs

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morgan 2025-01-16 13:34:01 +08:00
parent c6819ada5a
commit 8e8d873960
1 changed files with 5 additions and 5 deletions
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10
src/gateware/cxp_downconn.py
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@ -13,7 +13,7 @@ from functools import reduce
from operator import add from operator import add
class CXP_RXPHYs(Module, AutoCSR): class CXP_RXPHYs(Module, AutoCSR):
def __init__(self, refclk, pads, sys_clk_freq, master=0): def __init__(self, refclk, pads, sys_clk_freq, master):
self.qpll_reset = CSR() self.qpll_reset = CSR()
self.qpll_locked = CSRStatus() self.qpll_locked = CSRStatus()
self.gtx_start_init = CSRStorage() self.gtx_start_init = CSRStorage()
@ -295,13 +295,13 @@ class Comma_Aligner(Module):
class GTX(Module): class GTX(Module):
""" """
A reconfigurable linerate GTX with QPLL A linerate reconfigurable 40bit width GTX with QPLL
Designed for 12.5, 10, 6.25, 5, 3.125, 2.5, 1.25Gpbs Designed for 12.5, 10, 6.25, 5, 3.125, 2.5, 1.25Gpbs
To change the linerate: To change the linerate:
1) Change the VCO frequency 1) Change the QPLL VCO frequency
- 12.5, 6.25, 3.125Gbps: QPLL VCO @ 12.5GHz, - 12.5, 6.25, 3.125Gbps: VCO @ 12.5GHz,
- 10, 6.25, 5, 2.5, 1.25Gbps: QPLL VCO @ 10GHz - 10, 6.25, 5, 2.5, 1.25Gbps: VCO @ 10GHz
2) Update the xXOUT_DIV and TXUSRCLK frequency if using tx 2) Update the xXOUT_DIV and TXUSRCLK frequency if using tx
3) Reset the entire rx and tx 3) Reset the entire rx and tx
""" """