diff --git a/src/gateware/cxp_downconn.py b/src/gateware/cxp_downconn.py
index 188d7ae..45a1e5b 100644
--- a/src/gateware/cxp_downconn.py
+++ b/src/gateware/cxp_downconn.py
@@ -13,7 +13,7 @@ from functools import reduce
 from operator import add
 
 class CXP_RXPHYs(Module, AutoCSR):
-    def __init__(self, refclk, pads, sys_clk_freq, master=0):
+    def __init__(self, refclk, pads, sys_clk_freq, master):
         self.qpll_reset = CSR()
         self.qpll_locked = CSRStatus()
         self.gtx_start_init = CSRStorage()
@@ -295,13 +295,13 @@ class Comma_Aligner(Module):
 
 class GTX(Module):
     """
-    A reconfigurable linerate GTX with QPLL
+    A linerate reconfigurable 40bit width GTX with QPLL
     Designed for 12.5, 10, 6.25, 5, 3.125, 2.5, 1.25Gpbs
 
     To change the linerate:
-    1) Change the VCO frequency
-        - 12.5, 6.25, 3.125Gbps: QPLL VCO @ 12.5GHz,  
-        - 10, 6.25, 5, 2.5, 1.25Gbps: QPLL VCO @ 10GHz 
+    1) Change the QPLL VCO frequency
+        - 12.5, 6.25, 3.125Gbps: VCO @ 12.5GHz,  
+        - 10, 6.25, 5, 2.5, 1.25Gbps: VCO @ 10GHz 
     2) Update the xXOUT_DIV and TXUSRCLK frequency if using tx
     3) Reset the entire rx and tx
     """