forked from M-Labs/artiq-zynq
downconn GW: update docs
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@ -13,7 +13,7 @@ from functools import reduce
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from operator import add
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class CXP_RXPHYs(Module, AutoCSR):
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def __init__(self, refclk, pads, sys_clk_freq, master=0):
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def __init__(self, refclk, pads, sys_clk_freq, master):
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self.qpll_reset = CSR()
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self.qpll_locked = CSRStatus()
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self.gtx_start_init = CSRStorage()
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@ -295,13 +295,13 @@ class Comma_Aligner(Module):
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class GTX(Module):
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"""
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A reconfigurable linerate GTX with QPLL
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A linerate reconfigurable 40bit width GTX with QPLL
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Designed for 12.5, 10, 6.25, 5, 3.125, 2.5, 1.25Gpbs
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To change the linerate:
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1) Change the VCO frequency
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- 12.5, 6.25, 3.125Gbps: QPLL VCO @ 12.5GHz,
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- 10, 6.25, 5, 2.5, 1.25Gbps: QPLL VCO @ 10GHz
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1) Change the QPLL VCO frequency
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- 12.5, 6.25, 3.125Gbps: VCO @ 12.5GHz,
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- 10, 6.25, 5, 2.5, 1.25Gbps: VCO @ 10GHz
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2) Update the xXOUT_DIV and TXUSRCLK frequency if using tx
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3) Reset the entire rx and tx
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"""
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