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cxp GW: fix timinig

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cxp GW: improve timinig
This commit is contained in:
morgan 2025-01-23 17:22:16 +08:00
parent 6416dc6ea2
commit 8d9b030a24
1 changed files with 14 additions and 10 deletions
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24
src/gateware/cxp.py
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@ -116,7 +116,7 @@ class RX_Pipeline(Module, AutoCSR):
self.submodules.trig_ack_checker = trig_ack_checker = cdr(Trigger_Ack_Checker())
self.submodules.trig_ack_ps = trig_ack_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
self.sync.cxp_gtx_rx += trig_ack_ps.i.eq(trig_ack_checker.ack)
self.comb += trig_ack_ps.i.eq(trig_ack_checker.ack)
self.trig_ack = Signal()
self.trig_clr = Signal()
@ -138,7 +138,7 @@ class RX_Pipeline(Module, AutoCSR):
decode_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
buffer_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
self.submodules += decode_err_ps, buffer_err_ps
self.sync.cxp_gtx_rx += [
self.comb += [
decode_err_ps.i.eq(reader.decode_err),
buffer_err_ps.i.eq(reader.buffer_err),
]
@ -167,7 +167,7 @@ class RX_Pipeline(Module, AutoCSR):
self.test_packet_counter.status.eq(test_pak_cnt_sys),
]
self.submodules.test_reset_ps = test_reset_ps = PulseSynchronizer("sys", "cxp_gtx_rx")
self.sync += test_reset_ps.i.eq(self.test_counts_reset.re),
self.comb += test_reset_ps.i.eq(self.test_counts_reset.re),
test_err_cnt_rx = Signal.like(test_err_cnt_sys)
test_pak_cnt_rx = Signal.like(test_pak_cnt_sys)
@ -348,20 +348,24 @@ class CXP_Frame_Pipeline(Module, AutoCSR):
# CRC error counter
self.submodules.crc_reset_ps = crc_reset_ps = PulseSynchronizer("sys", "cxp_gtx_rx")
self.sync += crc_reset_ps.i.eq(self.crc_error_reset.re)
crc_error_r = Signal()
crc_error_cnt_rx = Signal.like(self.crc_error_cnt.status)
self.comb += crc_reset_ps.i.eq(self.crc_error_reset.re)
crc_error_cnt_rx = Signal.like(self.crc_error_cnt.status)
crc_error_cnt_sys = Signal.like(self.crc_error_cnt.status)
self.sync += self.crc_error_cnt.status.eq(crc_error_cnt_sys)
crc_error_r = Signal()
self.sync.cxp_gtx_rx += [
# to improve timinig
crc_error_r.eq(pixel_pipeline.crc_checker.error),
If(crc_error_r,
crc_error_cnt_rx.eq(crc_error_cnt_rx + 1),
).Elif(crc_reset_ps.o,
If(crc_reset_ps.o,
crc_error_cnt_rx.eq(crc_error_cnt_rx.reset),
).Elif(crc_error_r,
crc_error_cnt_rx.eq(crc_error_cnt_rx + 1),
),
]
self.specials += MultiReg(crc_error_cnt_rx, self.crc_error_cnt.status)
self.specials += MultiReg(crc_error_cnt_rx, crc_error_cnt_sys)
# RTIO interface