forked from M-Labs/artiq-zynq
downconn FW: remove phy setup & rename csr
This commit is contained in:
parent
4286820f4d
commit
8cafbb2471
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@ -2,25 +2,11 @@ use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
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use libboard_zynq::{println, timer::GlobalTimer};
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use libboard_zynq::{println, timer::GlobalTimer};
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use log::info;
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use log::info;
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// use log::info;
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use crate::{cxp_phys, cxp_proto, pl::csr::CXP};
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use crate::{cxp_proto,
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pl::{csr, csr::CXP}};
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#[derive(Clone, Copy, Debug)]
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pub fn loopback_testing(channel: usize, timer: &mut GlobalTimer, speed: cxp_phys::CXP_SPEED) {
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#[allow(non_camel_case_types)]
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pub enum CXP_SPEED {
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CXP_1,
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CXP_2,
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CXP_3,
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CXP_5,
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CXP_6,
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CXP_10,
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CXP_12,
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}
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pub fn loopback_testing(channel: usize, timer: &mut GlobalTimer, speed: CXP_SPEED) {
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println!("==============================================================================");
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println!("==============================================================================");
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cxp_gtx::change_linerate(channel, timer, speed);
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cxp_phys::change_linerate(channel, timer, speed);
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unsafe {
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unsafe {
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info!("waiting for tx&rx setup...");
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info!("waiting for tx&rx setup...");
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@ -71,8 +57,11 @@ pub fn loopback_testing(channel: usize, timer: &mut GlobalTimer, speed: CXP_SPEE
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(CXP[channel].downconn_trigger_ack_write)(1);
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(CXP[channel].downconn_trigger_ack_write)(1);
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info!("after clr trig ack = {}", (CXP[channel].downconn_trigger_ack_read)());
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info!("after clr trig ack = {}", (CXP[channel].downconn_trigger_ack_read)());
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info!("decoder error = {}", (CXP[channel].downconn_decoder_error_read)());
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info!(
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info!("test error = {}", (CXP[channel].downconn_test_error_read)());
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"decoder error = {}",
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(CXP[channel].downconn_bootstrap_decoder_err_read)()
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);
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info!("test error = {}", (CXP[channel].downconn_bootstrap_test_err_read)());
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info!("packet type = {:#06X}", (CXP[channel].downconn_packet_type_read)());
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info!("packet type = {:#06X}", (CXP[channel].downconn_packet_type_read)());
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cxp_proto::receive(channel).expect("loopback gtx rx error");
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cxp_proto::receive(channel).expect("loopback gtx rx error");
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@ -96,439 +85,3 @@ pub fn loopback_testing(channel: usize, timer: &mut GlobalTimer, speed: CXP_SPEE
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cxp_proto::print_packetu32(&pak_arr, &k_arr);
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cxp_proto::print_packetu32(&pak_arr, &k_arr);
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}
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}
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}
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}
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pub fn setup(timer: &mut GlobalTimer) {
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// TODO: do a for loop for channel?
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let channel: usize = 0;
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unsafe {
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info!("turning on pmc loopback mode...");
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(CXP[channel].downconn_loopback_mode_write)(0b010); // Near-End PMA Loopback
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// QPLL setup
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csr::cxp_phys::downconn_qpll_reset_write(1);
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info!("waiting for QPLL/CPLL to lock...");
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while csr::cxp_phys::downconn_qpll_locked_read() != 1 {}
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info!("QPLL locked");
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// tx/rx setup
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(CXP[channel].downconn_tx_start_init_write)(1);
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(CXP[channel].downconn_rx_start_init_write)(1);
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info!("waiting for tx & rx setup...");
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timer.delay_us(50_000);
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info!(
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"tx_phaligndone = {} | rx_phaligndone = {}",
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(CXP[channel].downconn_txinit_phaligndone_read)(),
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(CXP[channel].downconn_rxinit_phaligndone_read)(),
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);
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}
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cxp_gtx::change_linerate(channel, timer, CXP_SPEED::CXP_1);
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}
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pub mod cxp_gtx {
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use super::*;
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struct CdrConfig {
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pub cfg_reg0: u16, // addr = 0xA8
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pub cfg_reg1: u16, // addr = 0xA9
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pub cfg_reg2: u16, // addr = 0xAA
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pub cfg_reg3: u16, // addr = 0xAB
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pub cfg_reg4: u16, // addr = 0xAC
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}
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pub fn change_linerate(channel: usize, timer: &mut GlobalTimer, speed: CXP_SPEED) {
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info!("Changing datarate to {:?}", speed);
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// DEBUG: DRP pll for TXUSRCLK = freq(linerate)/20
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let settings = txusrclk::get_txusrclk_config(speed);
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txusrclk::setup(channel, timer, settings);
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change_qpll_fb_divider(speed);
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change_gtx_divider(channel, speed);
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change_cdr_cfg(channel, speed);
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unsafe {
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csr::cxp_phys::downconn_qpll_reset_write(1);
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info!("waiting for QPLL/CPLL to lock...");
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while csr::cxp_phys::downconn_qpll_locked_read() != 1 {}
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info!("QPLL locked");
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}
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unsafe {
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(CXP[channel].downconn_tx_restart_write)(1);
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(CXP[channel].downconn_rx_restart_write)(1);
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}
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}
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fn change_qpll_fb_divider(speed: CXP_SPEED) {
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let qpll_div_reg = match speed {
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CXP_SPEED::CXP_1 | CXP_SPEED::CXP_2 | CXP_SPEED::CXP_5 | CXP_SPEED::CXP_10 => 0x0120, // FB_Divider = 80
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CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 | CXP_SPEED::CXP_12 => 0x0170, // FB_Divider = 100
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};
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println!("0x36 = {:#06x}", qpll_read(0x36));
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qpll_write(0x36, qpll_div_reg);
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println!("0x36 = {:#06x}", qpll_read(0x36));
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}
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fn change_gtx_divider(channel: usize, speed: CXP_SPEED) {
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let div_reg = match speed {
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CXP_SPEED::CXP_1 => 0x33, // RXOUT_DIV = 8
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CXP_SPEED::CXP_2 | CXP_SPEED::CXP_3 => 0x22, // RXOUT_DIV = 4
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CXP_SPEED::CXP_5 | CXP_SPEED::CXP_6 => 0x11, // RXOUT_DIV = 2
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CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => 0x00, // RXOUT_DIV = 1
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};
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println!("0x88 = {:#06x}", gtx_read(channel, 0x88));
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gtx_write(channel, 0x88, div_reg);
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println!("0x88 = {:#06x}", gtx_read(channel, 0x88));
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}
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fn change_cdr_cfg(channel: usize, speed: CXP_SPEED) {
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let cdr_cfg = match speed {
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// when RXOUT_DIV = 8
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CXP_SPEED::CXP_1 => {
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CdrConfig {
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cfg_reg0: 0x0020, //0x0A8
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cfg_reg1: 0x1008, //0x0A9
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cfg_reg2: 0x23FF, //0x0AA
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cfg_reg3: 0x0000, //0x0AB
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cfg_reg4: 0x0003, //0x0AC
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}
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}
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// when RXOUT_DIV = 4
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CXP_SPEED::CXP_2 | CXP_SPEED::CXP_5 => {
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CdrConfig {
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cfg_reg0: 0x0020, //0x0A8
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cfg_reg1: 0x1010, //0x0A9
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cfg_reg2: 0x23FF, //0x0AA
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cfg_reg3: 0x0000, //0x0AB
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cfg_reg4: 0x0003, //0x0AC
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}
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}
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// when RXOUT_DIV= 2
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CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 => {
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CdrConfig {
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cfg_reg0: 0x0020, //0x0A8
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cfg_reg1: 0x1020, //0x0A9
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cfg_reg2: 0x23FF, //0x0AA
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cfg_reg3: 0x0000, //0x0AB
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cfg_reg4: 0x0003, //0x0AC
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}
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}
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// when RXOUT_DIV= 1
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CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => {
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CdrConfig {
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cfg_reg0: 0x0020, //0x0A8
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cfg_reg1: 0x1040, //0x0A9
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cfg_reg2: 0x23FF, //0x0AA
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cfg_reg3: 0x0000, //0x0AB
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cfg_reg4: 0x000B, //0x0AC
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}
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}
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};
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gtx_write(channel, 0x0A8, cdr_cfg.cfg_reg0);
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gtx_write(channel, 0x0A9, cdr_cfg.cfg_reg1);
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gtx_write(channel, 0x0AA, cdr_cfg.cfg_reg2);
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gtx_write(channel, 0x0AB, cdr_cfg.cfg_reg3);
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gtx_write(channel, 0x0AC, cdr_cfg.cfg_reg4);
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}
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#[allow(dead_code)]
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fn gtx_read(channel: usize, address: u16) -> u16 {
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unsafe {
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(CXP[channel].downconn_gtx_daddr_write)(address);
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(CXP[channel].downconn_gtx_dread_write)(1);
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while (CXP[channel].downconn_gtx_dready_read)() != 1 {}
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(CXP[channel].downconn_gtx_dout_read)()
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}
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}
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fn gtx_write(channel: usize, address: u16, value: u16) {
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unsafe {
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(CXP[channel].downconn_gtx_daddr_write)(address);
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(CXP[channel].downconn_gtx_din_write)(value);
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(CXP[channel].downconn_gtx_din_stb_write)(1);
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while (CXP[channel].downconn_gtx_dready_read)() != 1 {}
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}
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}
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#[allow(dead_code)]
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fn qpll_read(address: u8) -> u16 {
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unsafe {
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csr::cxp_phys::downconn_qpll_daddr_write(address);
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csr::cxp_phys::downconn_qpll_dread_write(1);
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while csr::cxp_phys::downconn_qpll_dready_read() != 1 {}
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csr::cxp_phys::downconn_qpll_dout_read()
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}
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}
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fn qpll_write(address: u8, value: u16) {
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unsafe {
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csr::cxp_phys::downconn_qpll_daddr_write(address);
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csr::cxp_phys::downconn_qpll_din_write(value);
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csr::cxp_phys::downconn_qpll_din_stb_write(1);
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while csr::cxp_phys::downconn_qpll_dready_read() != 1 {}
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}
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}
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}
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pub mod txusrclk {
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use super::*;
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pub struct PLLSetting {
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pub clkout0_reg1: u16, //0x08
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pub clkout0_reg2: u16, //0x09
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pub clkfbout_reg1: u16, //0x14
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pub clkfbout_reg2: u16, //0x15
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pub div_reg: u16, //0x16
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pub lock_reg1: u16, //0x18
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pub lock_reg2: u16, //0x19
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pub lock_reg3: u16, //0x1A
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pub power_reg: u16, //0x28
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pub filt_reg1: u16, //0x4E
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pub filt_reg2: u16, //0x4F
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}
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fn one_clock_cycle(channel: usize) {
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unsafe {
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(CXP[channel].downconn_pll_dclk_write)(1);
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(CXP[channel].downconn_pll_dclk_write)(0);
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}
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}
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fn set_addr(channel: usize, address: u8) {
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unsafe {
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(CXP[channel].downconn_pll_daddr_write)(address);
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}
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}
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fn set_data(channel: usize, value: u16) {
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unsafe {
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(CXP[channel].downconn_pll_din_write)(value);
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}
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}
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fn set_enable(channel: usize, en: bool) {
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unsafe {
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let val = if en { 1 } else { 0 };
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(CXP[channel].downconn_pll_den_write)(val);
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}
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}
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fn set_write_enable(channel: usize, en: bool) {
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unsafe {
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let val = if en { 1 } else { 0 };
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(CXP[channel].downconn_pll_dwen_write)(val);
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}
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}
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fn get_data(channel: usize) -> u16 {
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unsafe { (CXP[channel].downconn_pll_dout_read)() }
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}
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fn drp_ready(channel: usize) -> bool {
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unsafe { (CXP[channel].downconn_pll_dready_read)() == 1 }
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}
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#[allow(dead_code)]
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fn read(channel: usize, address: u8) -> u16 {
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set_addr(channel, address);
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set_enable(channel, true);
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// Set DADDR on the mmcm and assert DEN for one clock cycle
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one_clock_cycle(channel);
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set_enable(channel, false);
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while !drp_ready(channel) {
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// keep the clock signal until data is ready
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one_clock_cycle(channel);
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}
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get_data(channel)
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}
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fn write(channel: usize, address: u8, value: u16) {
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set_addr(channel, address);
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set_data(channel, value);
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set_write_enable(channel, true);
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set_enable(channel, true);
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// Set DADDR, DI on the mmcm and assert DWE, DEN for one clock cycle
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one_clock_cycle(channel);
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set_write_enable(channel, false);
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set_enable(channel, false);
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while !drp_ready(channel) {
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// keep the clock signal until write is finished
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one_clock_cycle(channel);
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}
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}
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fn reset(channel: usize, rst: bool) {
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unsafe {
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let val = if rst { 1 } else { 0 };
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(CXP[channel].downconn_txpll_reset_write)(val)
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}
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}
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pub fn setup(channel: usize, timer: &mut GlobalTimer, settings: PLLSetting) {
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if false {
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info!("0x08 = {:#06x}", read(channel, 0x08));
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info!("0x09 = {:#06x}", read(channel, 0x09));
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info!("0x14 = {:#06x}", read(channel, 0x14));
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info!("0x15 = {:#06x}", read(channel, 0x15));
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info!("0x16 = {:#06x}", read(channel, 0x16));
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info!("0x18 = {:#06x}", read(channel, 0x18));
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info!("0x19 = {:#06x}", read(channel, 0x19));
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info!("0x1A = {:#06x}", read(channel, 0x1A));
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info!("0x28 = {:#06x}", read(channel, 0x28));
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info!("0x4E = {:#06x}", read(channel, 0x4E));
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info!("0x4F = {:#06x}", read(channel, 0x4F));
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} else {
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// Based on "DRP State Machine" from XAPP888
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// hold reset HIGH during pll config
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reset(channel, true);
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write(channel, 0x08, settings.clkout0_reg1);
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write(channel, 0x09, settings.clkout0_reg2);
|
|
||||||
write(channel, 0x14, settings.clkfbout_reg1);
|
|
||||||
write(channel, 0x15, settings.clkfbout_reg2);
|
|
||||||
write(channel, 0x16, settings.div_reg);
|
|
||||||
write(channel, 0x18, settings.lock_reg1);
|
|
||||||
write(channel, 0x19, settings.lock_reg2);
|
|
||||||
write(channel, 0x1A, settings.lock_reg3);
|
|
||||||
write(channel, 0x28, settings.power_reg);
|
|
||||||
write(channel, 0x4E, settings.filt_reg1);
|
|
||||||
write(channel, 0x4F, settings.filt_reg2);
|
|
||||||
reset(channel, false);
|
|
||||||
|
|
||||||
// wait for the pll to lock
|
|
||||||
timer.delay_us(100);
|
|
||||||
|
|
||||||
let locked = unsafe { (CXP[channel].downconn_txpll_locked_read)() == 1 };
|
|
||||||
info!("txusrclk locked = {}", locked);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
pub fn get_txusrclk_config(speed: CXP_SPEED) -> PLLSetting {
|
|
||||||
match speed {
|
|
||||||
CXP_SPEED::CXP_1 => {
|
|
||||||
// CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 32
|
|
||||||
// TXUSRCLK=62.5MHz
|
|
||||||
PLLSetting {
|
|
||||||
clkout0_reg1: 0x1410, //0x08
|
|
||||||
clkout0_reg2: 0x0000, //0x09
|
|
||||||
clkfbout_reg1: 0x1104, //0x14
|
|
||||||
clkfbout_reg2: 0x0000, //0x15
|
|
||||||
div_reg: 0x1041, //0x16
|
|
||||||
lock_reg1: 0x03e8, //0x18
|
|
||||||
lock_reg2: 0x5801, //0x19
|
|
||||||
lock_reg3: 0xdbe9, //0x1A
|
|
||||||
power_reg: 0x0000, //0x28
|
|
||||||
filt_reg1: 0x9808, //0x4E
|
|
||||||
filt_reg2: 0x9100, //0x4F
|
|
||||||
}
|
|
||||||
}
|
|
||||||
CXP_SPEED::CXP_2 => {
|
|
||||||
// CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 16
|
|
||||||
// TXUSRCLK=62.5MHz
|
|
||||||
PLLSetting {
|
|
||||||
clkout0_reg1: 0x1208, //0x08
|
|
||||||
clkout0_reg2: 0x0000, //0x09
|
|
||||||
clkfbout_reg1: 0x1104, //0x14
|
|
||||||
clkfbout_reg2: 0x0000, //0x15
|
|
||||||
div_reg: 0x1041, //0x16
|
|
||||||
lock_reg1: 0x03e8, //0x18
|
|
||||||
lock_reg2: 0x5801, //0x19
|
|
||||||
lock_reg3: 0xdbe9, //0x1A
|
|
||||||
power_reg: 0x0000, //0x28
|
|
||||||
filt_reg1: 0x9808, //0x4E
|
|
||||||
filt_reg2: 0x9100, //0x4F
|
|
||||||
}
|
|
||||||
}
|
|
||||||
CXP_SPEED::CXP_3 => {
|
|
||||||
// CLKFBOUT_MULT = 10, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 16
|
|
||||||
// TXUSRCLK=78.125MHz
|
|
||||||
PLLSetting {
|
|
||||||
clkout0_reg1: 0x1208, //0x08
|
|
||||||
clkout0_reg2: 0x0000, //0x09
|
|
||||||
clkfbout_reg1: 0x1145, //0x14
|
|
||||||
clkfbout_reg2: 0x0000, //0x15
|
|
||||||
div_reg: 0x1041, //0x16
|
|
||||||
lock_reg1: 0x03e8, //0x18
|
|
||||||
lock_reg2: 0x7001, //0x19
|
|
||||||
lock_reg3: 0xf3e9, //0x1A
|
|
||||||
power_reg: 0x0000, //0x28
|
|
||||||
filt_reg1: 0x9908, //0x4E
|
|
||||||
filt_reg2: 0x1900, //0x4F
|
|
||||||
}
|
|
||||||
}
|
|
||||||
CXP_SPEED::CXP_5 => {
|
|
||||||
// CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 8
|
|
||||||
// TXUSRCLK=125MHz
|
|
||||||
PLLSetting {
|
|
||||||
clkout0_reg1: 0x1104, //0x08
|
|
||||||
clkout0_reg2: 0x0000, //0x09
|
|
||||||
clkfbout_reg1: 0x1104, //0x14
|
|
||||||
clkfbout_reg2: 0x0000, //0x15
|
|
||||||
div_reg: 0x1041, //0x16
|
|
||||||
lock_reg1: 0x03e8, //0x18
|
|
||||||
lock_reg2: 0x5801, //0x19
|
|
||||||
lock_reg3: 0xdbe9, //0x1A
|
|
||||||
power_reg: 0x0000, //0x28
|
|
||||||
filt_reg1: 0x9808, //0x4E
|
|
||||||
filt_reg2: 0x9100, //0x4F
|
|
||||||
}
|
|
||||||
}
|
|
||||||
CXP_SPEED::CXP_6 => {
|
|
||||||
// CLKFBOUT_MULT = 10, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 8
|
|
||||||
// TXUSRCLK=156.25MHz
|
|
||||||
PLLSetting {
|
|
||||||
clkout0_reg1: 0x1104, //0x08
|
|
||||||
clkout0_reg2: 0x0000, //0x09
|
|
||||||
clkfbout_reg1: 0x1145, //0x14
|
|
||||||
clkfbout_reg2: 0x0000, //0x15
|
|
||||||
div_reg: 0x1041, //0x16
|
|
||||||
lock_reg1: 0x03e8, //0x18
|
|
||||||
lock_reg2: 0x7001, //0x19
|
|
||||||
lock_reg3: 0xf3e9, //0x1A
|
|
||||||
power_reg: 0x0000, //0x28
|
|
||||||
filt_reg1: 0x9908, //0x4E
|
|
||||||
filt_reg2: 0x1900, //0x4F
|
|
||||||
}
|
|
||||||
}
|
|
||||||
CXP_SPEED::CXP_10 => {
|
|
||||||
// CLKFBOUT_MULT = 8, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 4
|
|
||||||
// TXUSRCLK=250MHz
|
|
||||||
PLLSetting {
|
|
||||||
clkout0_reg1: 0x1082, //0x08
|
|
||||||
clkout0_reg2: 0x0000, //0x09
|
|
||||||
clkfbout_reg1: 0x1104, //0x14
|
|
||||||
clkfbout_reg2: 0x0000, //0x15
|
|
||||||
div_reg: 0x1041, //0x16
|
|
||||||
lock_reg1: 0x03e8, //0x18
|
|
||||||
lock_reg2: 0x5801, //0x19
|
|
||||||
lock_reg3: 0xdbe9, //0x1A
|
|
||||||
power_reg: 0x0000, //0x28
|
|
||||||
filt_reg1: 0x9808, //0x4E
|
|
||||||
filt_reg2: 0x9100, //0x4F
|
|
||||||
}
|
|
||||||
}
|
|
||||||
CXP_SPEED::CXP_12 => {
|
|
||||||
// CLKFBOUT_MULT = 10, DIVCLK_DIVIDE = 1 , CLKOUT0_DIVIDE = 4
|
|
||||||
// TXUSRCLK=312.5MHz
|
|
||||||
PLLSetting {
|
|
||||||
clkout0_reg1: 0x1082, //0x08
|
|
||||||
clkout0_reg2: 0x0000, //0x09
|
|
||||||
clkfbout_reg1: 0x1145, //0x14
|
|
||||||
clkfbout_reg2: 0x0000, //0x15
|
|
||||||
div_reg: 0x1041, //0x16
|
|
||||||
lock_reg1: 0x03e8, //0x18
|
|
||||||
lock_reg2: 0x7001, //0x19
|
|
||||||
lock_reg3: 0xf3e9, //0x1A
|
|
||||||
power_reg: 0x0000, //0x28
|
|
||||||
filt_reg1: 0x9908, //0x4E
|
|
||||||
filt_reg2: 0x1900, //0x4F
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue