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cxp: add packet type inserter

This commit is contained in:
morgan 2024-08-30 16:25:19 +08:00
parent f23ce2ef70
commit 8c750c1993
1 changed files with 29 additions and 19 deletions
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48
src/gateware/cxp.py
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@ -82,18 +82,15 @@ def cxp_phy_layout():
class CXP_TX_Core(Module, AutoCSR):
def __init__(self, pmod_pads):
self.packet_type = CSRStorage(8)
self.din_len = CSRStorage(6)
self.din_pak = CSR(8)
self.din_k = CSRStorage()
self.din_ready = CSRStatus()
self.inc = CSR()
self.dout_pak = CSRStatus(8)
self.kout_pak = CSRStatus()
self.dout_valid =CSRStatus()
# # #
len = Signal(6, reset=1)
# a buf is used to simulated a proper endpoint which hold source.stb high as long as data is available
# otherwise, CSR.re only hold when CSR is written to and it cannot act as a proper source
@ -101,10 +98,17 @@ class CXP_TX_Core(Module, AutoCSR):
self.submodules.buf_out = buf_out = stream.SyncFIFO(cxp_phy_layout(), 64)
self.submodules.crc_inserter = crc_inserters = CXPCRC32Inserter(cxp_phy_layout())
self.submodules.pak_start = pak_start = Packet_Start_Inserter(cxp_phy_layout())
self.submodules.pak_end = pak_end = Packet_End_Inserter(cxp_phy_layout())
self.submodules.pak_type = pak_type = Code_Inserter(cxp_phy_layout())
self.submodules.pak_wrp = pak_wrp = Packet_Wrapper(cxp_phy_layout())
self.comb += [
pak_type.data.eq(self.packet_type.storage),
pak_type.k.eq(0),
]
len = Signal(6, reset=1)
self.sync += [
# input
self.din_ready.status.eq(buf_in.sink.ack),
buf_in.sink.stb.eq(0),
@ -120,7 +124,21 @@ class CXP_TX_Core(Module, AutoCSR):
buf_in.sink.data.eq(self.din_pak.r),
buf_in.sink.k.eq(self.din_k.storage),
),
]
tx_pipeline = [ buf_in, crc_inserters, pak_type, pak_wrp, buf_out]
for s, d in zip(tx_pipeline, tx_pipeline[1:]):
self.comb += s.source.connect(d.sink)
# DEBUG
self.inc = CSR()
self.dout_pak = CSRStatus(8)
self.kout_pak = CSRStatus()
self.dout_valid =CSRStatus()
self.sync += [
# output
buf_out.source.ack.eq(self.inc.re),
self.dout_pak.status.eq(buf_out.source.data),
@ -128,21 +146,13 @@ class CXP_TX_Core(Module, AutoCSR):
self.dout_valid.status.eq(buf_out.source.stb),
]
tx_pipeline = [ buf_in, crc_inserters, pak_start, pak_end, buf_out]
for s, d in zip(tx_pipeline, tx_pipeline[1:]):
self.comb += s.source.connect(d.sink)
# DEBUG
self.specials += [
# # pmod 0-7 pin
Instance("OBUF", i_I=pak_start.sink.stb, o_O=pmod_pads[0]),
Instance("OBUF", i_I=pak_start.sink.ack, o_O=pmod_pads[1]),
Instance("OBUF", i_I=pak_start.source.stb, o_O=pmod_pads[2]),
Instance("OBUF", i_I=pak_start.source.ack, o_O=pmod_pads[3]),
Instance("OBUF", i_I=buf_in.sink.stb, o_O=pmod_pads[0]),
Instance("OBUF", i_I=buf_in.sink.ack, o_O=pmod_pads[1]),
Instance("OBUF", i_I=buf_in.source.stb, o_O=pmod_pads[2]),
Instance("OBUF", i_I=buf_in.source.ack, o_O=pmod_pads[3]),
Instance("OBUF", i_I=buf_out.sink.stb, o_O=pmod_pads[4]),
Instance("OBUF", i_I=buf_out.sink.ack, o_O=pmod_pads[5]),
Instance("OBUF", i_I=buf_out.source.stb, o_O=pmod_pads[6]),