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cxp downconn: fix bruteforcealigner

This commit is contained in:
morgan 2024-07-26 16:24:18 +08:00
parent 4ba1c5ef2e
commit 865434763d
1 changed files with 11 additions and 10 deletions
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21
src/gateware/cxp_downconn.py
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@ -8,7 +8,6 @@ from misoc.interconnect.csr import *
from artiq.gateware.drtio.transceiver.gtx_7series_init import * from artiq.gateware.drtio.transceiver.gtx_7series_init import *
from operator import add from operator import add
from math import ceil
from functools import reduce from functools import reduce
# Changes the phase of the transceiver RX clock to align the comma to # Changes the phase of the transceiver RX clock to align the comma to
@ -28,17 +27,16 @@ from functools import reduce
# Warning: Xilinx transceivers are LSB first, and comma needs to be flipped # Warning: Xilinx transceivers are LSB first, and comma needs to be flipped
# compared to the usual 8b10b binary representation. # compared to the usual 8b10b binary representation.
class CXP_BruteforceClockAligner(Module): class CXP_BruteforceClockAligner(Module):
def __init__(self, comma, sys_clk_freq, check_period): def __init__(self, comma, check_max_val):
self.rxdata = Signal(20) self.rxdata = Signal(20)
self.restart = Signal() self.restart = Signal()
self.ready = Signal() self.ready = Signal()
check_max_val = ceil(check_period*sys_clk_freq)
check_counter = Signal(max=check_max_val+1) check_counter = Signal(max=check_max_val+1)
check = Signal() check = Signal()
reset_check_counter = Signal() reset_check_counter = Signal()
self.sync += [ self.sync.cxp_gtx_tx += [
check.eq(0), check.eq(0),
If(reset_check_counter, If(reset_check_counter,
check_counter.eq(check_max_val) check_counter.eq(check_max_val)
@ -52,7 +50,7 @@ class CXP_BruteforceClockAligner(Module):
) )
] ]
checks_reset = PulseSynchronizer("sys", "cxp_gtx_rx") checks_reset = PulseSynchronizer("cxp_gtx_tx", "cxp_gtx_rx")
self.submodules += checks_reset self.submodules += checks_reset
comma_n = ~comma & 0b1111111111 comma_n = ~comma & 0b1111111111
@ -81,7 +79,7 @@ class CXP_BruteforceClockAligner(Module):
) )
] ]
fsm = FSM(reset_state="WAIT_COMMA") fsm = ClockDomainsRenamer("cxp_gtx_tx")(FSM(reset_state="WAIT_COMMA"))
self.submodules += fsm self.submodules += fsm
fsm.act("WAIT_COMMA", fsm.act("WAIT_COMMA",
@ -130,7 +128,7 @@ class CXP_DownConn(Module):
assert tx_mode in ["single", "master", "slave"] assert tx_mode in ["single", "master", "slave"]
assert rx_mode in ["single", "master", "slave"] assert rx_mode in ["single", "master", "slave"]
cpll_div = 5 cpll_div = 4
cpll_div45 = 5 cpll_div45 = 5
refclk_div = 1 refclk_div = 1
Xxout_div = 2 Xxout_div = 2
@ -162,7 +160,7 @@ class CXP_DownConn(Module):
# TX generates cxp_tx clock, init must be in system domain # TX generates cxp_tx clock, init must be in system domain
self.submodules.tx_init = tx_init = GTXInit(sys_clk_freq, False, mode=tx_mode) self.submodules.tx_init = tx_init = GTXInit(sys_clk_freq, False, mode=tx_mode)
# RX receives restart commands from RTIO domain # RX receives restart commands from RTIO domain
self.submodules.rx_init = rx_init = GTXInit(sys_clk_freq, True, mode=rx_mode) self.submodules.rx_init = rx_init = ClockDomainsRenamer("cxp_gtx_tx")(GTXInit(sys_clk_freq, True, mode=rx_mode))
self.comb += [ self.comb += [
cpllreset.eq(tx_init.cpllreset), cpllreset.eq(tx_init.cpllreset),
tx_init.cplllock.eq(cplllock), tx_init.cplllock.eq(cplllock),
@ -422,8 +420,11 @@ class CXP_DownConn(Module):
self.decoders[1].input.eq(rxdata[10:]) self.decoders[1].input.eq(rxdata[10:])
] ]
# 6e-3 is too slow for 3.25Gbps line rate # 62.5MHz: cannot align
clock_aligner = CXP_BruteforceClockAligner(0b0101111100, sys_clk_freq, check_period=1e-2) # 125MHz: align <1s
# 156.25MHz: align <15s
# 250MHz: cannot align
clock_aligner = CXP_BruteforceClockAligner(0b0101111100, 1_000_000)
self.submodules += clock_aligner self.submodules += clock_aligner
self.comb += [ self.comb += [
clock_aligner.rxdata.eq(rxdata), clock_aligner.rxdata.eq(rxdata),