sim: update fns

sim_arbiter.py

@@ -12,7 +12,7 @@ class Frame_Pipeline(Module):
     def __init__(self, n_downconn, n_buffer=2):
         # to construct correct crc and ack/stb signal
         self.sinks = []
-        self.downconn_source = []
+        self.downconn = []
         for i in range(n_downconn):
             # generating the packet
             buffer = stream.SyncFIFO(word_layout, 32)
@@ -25,19 +25,19 @@ class Frame_Pipeline(Module):
             for s, d in zip(pipeline, pipeline[1:]):
                 self.comb += s.source.connect(d.sink)
             self.sinks.append(pipeline[0].sink)
-            self.downconn_source.append(pipeline[-1].source)
+            self.downconn.append(pipeline[-1])
 
 
-        self.buffer_sinks = []
+        self.buffers = []
         for i in range(n_buffer):
             # it should be mem block not "cycle buffer"
-            buf = DChar_Dropper()
+            buf = Buffer(word_layout_dchar)
             self.submodules += buf
             self.sync += buf.source.ack.eq(1) # no backpressure for sim
 
-            self.buffer_sinks.append(buf.sink)
+            self.buffers.append(buf)
         
-        self.submodules.router = Frame_Packet_Router(self.downconn_source, self.buffer_sinks,packet_size=16384)
+        self.submodules.router = Frame_Packet_Router(self.downconn, self.buffers ,packet_size=16384)
 
 
 
@@ -50,7 +50,7 @@ def packet_sim(packets=[], active_ch=2):
     assert active_ch <= CXP_CHANNELS
 
     print("=================TEST========================")
-    yield dut.router.active_src_mask.eq(active_ch - 1)
+    yield dut.router.n_ext_active.eq(active_ch - 1)
     sinks = dut.sinks
 
     cyc = len(packets[0])

sim_double_buffer.py

@@ -9,9 +9,9 @@ from src.gateware.cxp_pipeline import *
 class double_buffer_pipeline(Module):
     def __init__(self):
         fifo = stream.SyncFIFO(word_layout_dchar, 32)
-        double_buffer = Double_Stream_Buffer(0x100)
+        double_buffer = CXPCRC32_Checker(0x100)
         dchar_dropper = DChar_Dropper()
-        pipeline = [fifo, double_buffer, dchar_dropper]
+        pipeline = [double_buffer, dchar_dropper]
         self.submodules += pipeline
 
         for s, d in zip(pipeline, pipeline[1:]):

sim_eop.py

@@ -9,7 +9,7 @@ from src.gateware.cxp_pipeline import *
 class EOP_Pipeline(Module):
     def __init__(self):
         dchar_decoder = Duplicated_Char_Decoder()
-        eop_inserter = EOP_Inserter()
+        eop_inserter = EOP_Marker()
         buffer = stream.SyncFIFO(word_layout_dchar, 32)
         pipeline = [dchar_decoder, eop_inserter, buffer]
         self.submodules += pipeline

sim_frame.py

@@ -21,7 +21,7 @@ class Frame(Module):
         # NOTE: eop is needed for crc to work correctly and RX_Bootstrap need to be followed by a EOP marker anyway
         self.submodules.eop_marker = eop_marker = EOP_Marker()
 
-        self.submodules.stream_pipe = stream_pipe = Stream_Pipeline()
+        self.submodules.stream_pipe = stream_pipe = ROI_Pipeline()
 
         pipeline = [buffer, crc_inserter, dchar_decoder, eop_marker, stream_pipe]
         for s, d in zip(pipeline, pipeline[1:]):

sim_stream.py

@@ -28,7 +28,7 @@ class Pipeline(Module):
     def __init__(self):
         self.submodules.generator = generator = StreamData_Generator()
         self.submodules.dchar_decoder = dchar_decoder = Duplicated_Char_Decoder()
-        self.submodules.data_decoder = data_decoder = RX_Bootstrap()
+        self.submodules.data_decoder = data_decoder = Control_Packet_Reader()
         self.submodules.eop_marker = eop_marker = EOP_Marker()
 
         # # #