morgan/artiq-zynq
1
0
Fork 0
forked from M-Labs/artiq-zynq
Code Pull Requests Activity

zc706: fix compilation error

Browse Source
This commit is contained in:
morgan 2025-01-16 14:40:33 +08:00
parent a427874a3c
commit 845af45bfd
1 changed files with 15 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
src/gateware/zc706.py
View File

@ -689,6 +689,7 @@ class CXP_FMC():
clk_freq = 125e6
links = 4
master_ch = 0
cxp_downconn_pads = [platform.request("CXP_HS", i) for i in range(links)]
cxp_upconn_pads = [platform.request("CXP_LS", i) for i in range(links)]
@ -698,6 +699,7 @@ class CXP_FMC():
upconn_pads=cxp_upconn_pads,
downconn_pads=cxp_downconn_pads,
sys_clk_freq=clk_freq,
master=master_ch,
)
self.csr_devices.append("cxp_phys")
@ -705,24 +707,25 @@ class CXP_FMC():
rtio_channels = []
cxp_csr_group = []
cxp_mem_group = []
cxp_rx_pipelines = []
cxp_core_pipelines = []
for i, phy in enumerate(cxp_phys.phys):
cxp_name = "cxp" + str(i)
if i == 0:
cxp_interface = cxp.CXP_Master(phy, debug_sma_pad, pmod_pads)
# if i == 0:
# cxp_interface = cxp.CXP_Master(phy, debug_sma_pad, pmod_pads)
# Add rtlink for Master Connection only
print("CoaXPress at RTIO channel 0x{:06x}".format(len(rtio_channels)))
rtio_channels.append(rtio.Channel.from_phy(cxp_interface))
else:
cxp_interface = cxp.CXP_Extension(phy)
# # Add rtlink for Master Connection only
# print("CoaXPress at RTIO channel 0x{:06x}".format(len(rtio_channels)))
# rtio_channels.append(rtio.Channel.from_phy(cxp_interface))
# else:
# cxp_interface = cxp.CXP_Extension(phy)
cxp_interface = cxp.CXP_Core(phy)
setattr(self.submodules, cxp_name, cxp_interface)
self.csr_devices.append(cxp_name)
cxp_csr_group.append(cxp_name)
cxp_rx_pipelines.append(cxp_interface.get_rx_pipeline())
cxp_core_pipelines.append(cxp_interface)
# Add memory group
@ -737,8 +740,10 @@ class CXP_FMC():
self.add_memory_group("cxp_mem", cxp_mem_group)
self.add_csr_group("cxp", cxp_csr_group)
self.submodules.cxp_frame_pipeline = cxp.CXP_Frame_Pipeline(cxp_rx_pipelines, pmod_pads)
self.submodules.cxp_frame_pipeline = cxp_frame_pipeline = cxp.CXP_Frame_Pipeline(cxp_core_pipelines, pmod_pads, master=master_ch)
self.csr_devices.append("cxp_frame_pipeline")
print("CoaXPress at RTIO channel 0x{:06x}".format(len(rtio_channels)))
rtio_channels.append(rtio.Channel.from_phy(cxp_frame_pipeline ))