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zc706 GW: fix compilation err

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morgan 2025-01-14 13:04:26 +08:00
parent ec84a332c7
commit 844f2dab70
1 changed files with 1 additions and 1 deletions
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src/gateware/zc706.py
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@ -747,7 +747,7 @@ class CXP_FMC():
# max freq of cxp_gtx_rx = linerate/internal_datawidth = 12.5Gbps/40 = 312.5MHz
# zc706 use speed grade 2 which only support up to 10.3125Gbps (4ns)
# pushing to 12.5Gbps (3.2ns) will result in Pulse width violation but setup/hold times are met
rx = cxp_phys.downconn.rx_phys[0]
rx = cxp_phys.phys[0].rx
platform.add_period_constraint(rx.gtx.cd_cxp_gtx_tx.clk, 3.2)
platform.add_period_constraint(rx.gtx.cd_cxp_gtx_rx.clk, 3.2)
# constraint the CLK path