diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py
index 9d6b983..4c26c35 100755
--- a/src/gateware/zc706.py
+++ b/src/gateware/zc706.py
@@ -747,7 +747,7 @@ class CXP_FMC():
         # max freq of cxp_gtx_rx = linerate/internal_datawidth = 12.5Gbps/40 = 312.5MHz
         # zc706 use speed grade 2 which only support up to 10.3125Gbps (4ns)
         # pushing to 12.5Gbps (3.2ns) will result in Pulse width violation but setup/hold times are met
-        rx = cxp_phys.downconn.rx_phys[0]
+        rx = cxp_phys.phys[0].rx
         platform.add_period_constraint(rx.gtx.cd_cxp_gtx_tx.clk, 3.2)
         platform.add_period_constraint(rx.gtx.cd_cxp_gtx_rx.clk, 3.2)
         # constraint the CLK path