forked from M-Labs/artiq-zynq
cxp downconn fw: replace tx/rx rate with DRP
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@ -172,19 +172,22 @@ pub mod cxp_gtx {
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CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 | CXP_SPEED::CXP_12 => 0x0170, // FB_Divider = 100
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};
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println!("0x36 = {:#06x}", qpll_read(0x36));
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qpll_write(0x36, qpll_div_reg);
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println!("0x36 = {:#06x}", qpll_read(0x36));
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let rxout_div = match speed {
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CXP_SPEED::CXP_1 => 0b100, // 8
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CXP_SPEED::CXP_2 | CXP_SPEED::CXP_3 => 0b011, // 4
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CXP_SPEED::CXP_5 | CXP_SPEED::CXP_6 => 0b010, // 2
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CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => 0b001, // 1
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// DEBUG: remove txoutdiv
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let txrxout_div = match speed {
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CXP_SPEED::CXP_1 => 0x33, // 8
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CXP_SPEED::CXP_2 | CXP_SPEED::CXP_3 => 0x22, // 4
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CXP_SPEED::CXP_5 | CXP_SPEED::CXP_6 => 0x11, // 2
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CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => 0x00, // 1
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};
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unsafe {
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csr::cxp::downconn_rx_div_write(rxout_div);
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csr::cxp::downconn_tx_div_write(rxout_div);
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}
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// OUT_DIV
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println!("0x88 = {:#06x}", gtx_read(0x88));
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gtx_write(0x88, txrxout_div);
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println!("0x88 = {:#06x}", gtx_read(0x88));
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}
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fn change_cdr_cfg(speed: CXP_SPEED) {
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