forked from M-Labs/artiq-zynq
sim: update roi
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@ -12,7 +12,7 @@ class ROI(Module):
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fifo = stream.SyncFIFO(word_layout, 32) # to avoid data getting eaten and act as delay between eop
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dchar_decoder = Duplicated_Char_Decoder()
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# self.crc = CXPCRC32_Checker()
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self.pipeline = ROI_Pipeline()
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self.pipeline = Pixel_Pipeline(24, 32)
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pipeline = [fifo, dchar_decoder, self.pipeline]
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self.submodules += pipeline
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@ -76,6 +76,10 @@ def packet_sim(packets=[]):
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for name in img_header_layout:
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print(f"{name} = {yield getattr(metadata, name):#04X} ", end="")
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print()
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roi = dut.pipeline.roi
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print(f"x0 = {yield roi.cfg.x0} y0 = {yield roi.cfg.y0} | x1 = {yield roi.cfg.x1} y1 = {yield roi.cfg.y1}")
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print(f"out count = {yield roi.out.count}")
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assert True
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