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sim: update roi

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morgan 2025-01-15 16:21:30 +08:00
parent 69a84175b0
commit 7c51eb3de9
1 changed files with 5 additions and 1 deletions
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6
sim_roi.py
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@ -12,7 +12,7 @@ class ROI(Module):
fifo = stream.SyncFIFO(word_layout, 32) # to avoid data getting eaten and act as delay between eop fifo = stream.SyncFIFO(word_layout, 32) # to avoid data getting eaten and act as delay between eop
dchar_decoder = Duplicated_Char_Decoder() dchar_decoder = Duplicated_Char_Decoder()
# self.crc = CXPCRC32_Checker() # self.crc = CXPCRC32_Checker()
self.pipeline = ROI_Pipeline() self.pipeline = Pixel_Pipeline(24, 32)
pipeline = [fifo, dchar_decoder, self.pipeline] pipeline = [fifo, dchar_decoder, self.pipeline]
self.submodules += pipeline self.submodules += pipeline
@ -76,6 +76,10 @@ def packet_sim(packets=[]):
for name in img_header_layout: for name in img_header_layout:
print(f"{name} = {yield getattr(metadata, name):#04X} ", end="") print(f"{name} = {yield getattr(metadata, name):#04X} ", end="")
print() print()
roi = dut.pipeline.roi
print(f"x0 = {yield roi.cfg.x0} y0 = {yield roi.cfg.y0} | x1 = {yield roi.cfg.x1} y1 = {yield roi.cfg.y1}")
print(f"out count = {yield roi.out.count}")
assert True assert True