forked from M-Labs/artiq-zynq
cxp frame pipeline: frame handling pipeline
pipeline: add eop marker, cxp_crc32 checker frame: add stream crossbar, double buffer, parser frame: add metadata parser, frame extractor
This commit is contained in:
parent
3de7f403eb
commit
7baf2f9393
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from migen import *
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from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine
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from cxp_pipeline import *
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# from src.gateware.cxp_pipeline import * # for sim only
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from types import SimpleNamespace
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class EOP_Marker(Module):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout_dchar)
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self.source = stream.Endpoint(word_layout_dchar)
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# # #
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last_stb = Signal()
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self.sync += [
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If((~self.source.stb | self.source.ack),
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self.source.stb.eq(self.sink.stb),
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self.source.payload.eq(self.sink.payload),
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),
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last_stb.eq(self.sink.stb),
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]
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self.comb += [
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self.sink.ack.eq(~self.source.stb | self.source.ack),
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self.source.eop.eq(~self.sink.stb & last_stb),
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]
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class Streams_Crossbar(Module):
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def __init__(self, downconn_sources, stream_sinks):
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n_downconn = len(downconn_sources)
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self.active_conn= C(n_downconn)
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# TODO: change self.active_conns to signal and link it to rx_ready of GTX lanes
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# # #
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self.submodules.mux = mux = stream.Multiplexer(word_layout_dchar, n_downconn)
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for i, downconn in enumerate(downconn_sources):
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self.comb += downconn.source.connect(getattr(mux, "sink"+str(i)))
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self.submodules.fsm = fsm = FSM(reset_state="WAIT_HEADER")
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self.stream_id = Signal(char_width)
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case = dict((i, mux.source.connect(b.sink)) for i, b in enumerate(stream_sinks))
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fsm.act(
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"WAIT_HEADER",
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NextValue(self.stream_id, mux.source.dchar),
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If(mux.source.stb,
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NextState("COPY"),
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),
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)
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fsm.act(
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"COPY",
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Case(self.stream_id, case),
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If(mux.source.eop,
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NextState("SWITCH_CONN"),
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),
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)
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# Section 9.5.5 (CXP-001-2021)
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# When Multiple connections are active, stream packets are transmitted in
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# ascending order of Connection ID. And one connection shall be transmitting data at a time.
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read_mask = Signal(max=n_downconn)
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self.comb += mux.sel.eq(read_mask)
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fsm.act(
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"SWITCH_CONN",
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# assuming downconn_sources have ascending Connection ID
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If(read_mask == self.active_conn - 1,
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NextValue(read_mask, read_mask.reset),
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).Else(
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NextValue(read_mask, read_mask + 1),
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),
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NextState("WAIT_HEADER"),
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)
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def reverse_bytes(s):
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assert len(s) % 8 == 0
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char = [s[i*8:(i+1)*8] for i in range(len(s)//8)]
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return Cat(char[::-1])
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@ResetInserter()
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@CEInserter()
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class CXPCRC32(Module):
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# Section 9.2.2.2 (CXP-001-2021)
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width = 32
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polynom = 0x04C11DB7
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seed = 2**width - 1
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check = 0x00000000
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def __init__(self, data_width):
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self.data = Signal(data_width)
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self.value = Signal(self.width)
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self.error = Signal()
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# # #
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self.submodules.engine = LiteEthMACCRCEngine(
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data_width, self.width, self.polynom
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)
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reg = Signal(self.width, reset=self.seed)
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self.sync += reg.eq(self.engine.next)
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self.comb += [
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# the CRC Engine use Big Endian, need to reverse the bytes
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self.engine.data.eq(reverse_bytes(self.data)),
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self.engine.last.eq(reg),
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self.value.eq(reverse_bytes(reg[::-1])),
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self.error.eq(reg != self.check),
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]
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# For verifying crc in stream data packet
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class Double_Stream_Buffer(Module):
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def __init__(self, size):
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self.sink = stream.Endpoint(word_layout_dchar)
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self.submodules.crc = crc = CXPCRC32(word_dw)
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self.comb += crc.data.eq(self.sink.data)
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self.submodules.fsm = fsm = FSM(reset_state="RESET")
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write_mask = Signal()
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self.submodules.line_buffer0 = line_buffer0 = ResetInserter()(stream.SyncFIFO(word_layout_dchar, 2**bits_for(size//word_dw)))
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self.submodules.line_buffer1 = line_buffer1 = ResetInserter()(stream.SyncFIFO(word_layout_dchar, 2**bits_for(size//word_dw)))
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fsm.act("RESET",
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Case(write_mask,
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{
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0: line_buffer0.reset.eq(1),
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1: line_buffer1.reset.eq(1),
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}
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),
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crc.reset.eq(1),
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NextState("CHECKING"),
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)
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fsm.act("CHECKING",
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self.sink.ack.eq(1),
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If(self.sink.stb,
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crc.ce.eq(1),
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If(self.sink.eop,
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# discard the crc at the end
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NextState("SWITCH_BUFFER")
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).Else(
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If(write_mask == 0,
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self.sink.connect(line_buffer0.sink),
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).Else(
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self.sink.connect(line_buffer1.sink),
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),
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)
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)
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)
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# only valid data will be passed to downstream
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fsm.act("SWITCH_BUFFER",
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If(~crc.error,
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NextValue(write_mask, ~write_mask),
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),
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NextState("RESET"),
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)
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self.submodules.mux = mux = stream.Multiplexer(word_layout_dchar, 2)
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self.comb += [
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line_buffer0.source.connect(mux.sink0),
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line_buffer1.source.connect(mux.sink1),
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mux.sel.eq(~write_mask),
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]
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self.source = mux.source
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# DEBUG:
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self.write = Signal()
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self.error = Signal()
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self.comb += [
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self.write.eq(write_mask),
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self.error.eq(crc.error),
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]
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# # to add eop in the same cycle
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# # the tricks relies on the fact source lags sink one cycle
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# # but fsm .connect by default use combinational logic which the same cycle rising/falling edge check immpossible
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# fsm.act("CHECKING",
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# NextValue(self.source.payload.raw_bits(), 0),
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# NextValue(self.source.stb, 0),
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# If(self.sink.stb,
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# crc.ce.eq(1),
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# If(self.sink.eop,
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# NextState("RESET")
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# ).Else(
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# NextValue(self.source.payload.raw_bits(), self.sink.payload.raw_bits()),
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# NextValue(self.source.stb, 1),
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# )
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# )
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# )
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# last_eop = Signal()
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# self.comb += self.source.eop.eq(~last_eop & self.sink.eop)
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class Stream_Parser(Module):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout_dchar)
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self.source = stream.Endpoint(word_layout_dchar)
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# # #
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self.stream_id = Signal(char_width)
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self.pak_tag = Signal(char_width)
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self.stream_pak_size = Signal(char_width * 2)
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self.submodules.fsm = fsm = FSM(reset_state="WAIT_HEADER")
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fsm.act(
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"WAIT_HEADER",
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NextValue(self.stream_id, self.stream_id.reset),
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NextValue(self.pak_tag, self.pak_tag.reset),
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NextValue(self.stream_pak_size, self.stream_pak_size.reset),
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self.sink.ack.eq(1),
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If(
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self.sink.stb,
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NextValue(self.stream_id, self.sink.dchar),
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NextState("GET_PAK_TAG"),
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),
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)
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fsm.act(
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"GET_PAK_TAG",
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self.sink.ack.eq(1),
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If(
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self.sink.stb,
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NextValue(self.pak_tag, self.sink.dchar),
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NextState("GET_PAK_SIZE_0"),
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),
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)
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fsm.act(
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"GET_PAK_SIZE_0",
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self.sink.ack.eq(1),
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If(
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self.sink.stb,
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NextValue(self.stream_pak_size[8:], self.sink.dchar),
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NextState("GET_PAK_SIZE_1"),
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),
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)
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fsm.act(
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"GET_PAK_SIZE_1",
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self.sink.ack.eq(1),
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If(
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self.sink.stb,
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NextValue(self.stream_pak_size[:8], self.sink.dchar),
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NextState("STORE_BUFFER"),
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),
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)
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fsm.act(
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"STORE_BUFFER",
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self.sink.connect(self.source),
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# both serve the same function but using the pak size I can remove eop injecter and save 1 cycle
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If(self.sink.stb,
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NextValue(self.stream_pak_size, self.stream_pak_size - 1),
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If(self.stream_pak_size == 1,
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NextState("WAIT_HEADER"),
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)
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),
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)
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class Frame_Extractor(Module):
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def __init__(self, pixel_format="mono16"):
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assert pixel_format in ["mono16"]
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pixel_format = {
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"mono16": C(0x0105, 2*char_width)
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}
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self.format_error = Signal()
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self.decode_err = Signal()
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self.new_frame = Signal()
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self.new_line = Signal()
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n_metadata_chars = 23
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img_header_layout = [
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("stream_id", char_width),
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("source_tag", 2*char_width),
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("x_size", 3*char_width),
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("x_offset", 3*char_width),
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("y_size", 3*char_width),
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("y_offset", 3*char_width),
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("l_size", 3*char_width), # number of data words per image line
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("pixel_format", 2*char_width),
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("tap_geo", 2*char_width),
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("flag", char_width),
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]
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assert layout_len(img_header_layout) == n_metadata_chars*char_width
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# # #
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# TODO: decode Image header, line break
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self.sink = stream.Endpoint(word_layout_dchar)
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self.source = stream.Endpoint(word_layout_dchar)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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# DEBUG: remove this
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self.fsm_state = Signal()
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self.comb += self.fsm_state.eq(fsm.ongoing("IDLE"))
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fsm.act("IDLE",
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self.sink.ack.eq(1),
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If((self.sink.stb & (self.sink.dchar == KCode["stream_marker"]) & (self.sink.dchar_k == 1)),
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NextState("DECODE"),
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)
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)
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fsm.act("COPY",
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# until for new line or new frame
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If((self.sink.stb & (self.sink.dchar == KCode["stream_marker"]) & (self.sink.dchar_k == 1)),
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self.sink.ack.eq(1),
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NextState("DECODE"),
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).Else(
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self.sink.connect(self.source),
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)
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)
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type = {
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"new_frame": 0x01,
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"line_break": 0x02,
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}
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cnt = Signal(max=n_metadata_chars)
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fsm.act("DECODE",
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self.sink.ack.eq(1),
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If(self.sink.stb,
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Case(self.sink.dchar, {
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type["new_frame"]: [
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self.new_frame.eq(1),
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NextValue(cnt, cnt.reset),
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NextState("GET_FRAME_DATA"),
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],
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type["line_break"]: [
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self.new_line.eq(1),
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NextState("COPY"),
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],
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"default": [
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self.decode_err.eq(1),
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# discard all data until valid frame
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NextState("IDLE"),
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],
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}),
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)
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)
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packet_buffer = Signal(layout_len(img_header_layout))
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case = dict(
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(i, NextValue(packet_buffer[8*i:8*(i+1)], self.sink.dchar))
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for i in range(n_metadata_chars)
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)
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fsm.act("GET_FRAME_DATA",
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self.sink.ack.eq(1),
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If(self.sink.stb,
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Case(cnt, case),
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If(cnt == n_metadata_chars - 1,
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NextState("COPY"),
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NextValue(cnt, cnt.reset),
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).Else(
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NextValue(cnt, cnt + 1),
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),
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),
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)
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# dissect packet
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self.metadata = SimpleNamespace()
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idx = 0
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for name, size in img_header_layout:
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# CXP use MSB even when sending duplicate chars
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setattr(self.metadata, name, reverse_bytes(packet_buffer[idx:idx+size]))
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idx += size
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class Pixel_Decoder(Module):
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def __init__(self, pixel_format="mono16"):
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assert pixel_format == "mono16"
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self.sink = stream.Endpoint(word_layout_dchar)
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self.source = stream.Endpoint(word_layout_dchar)
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# # #
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# TODO: support mono16 for now?
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# TODO: or support it in driver instead?
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class Stream_Pipeline(Module):
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# optimal stream packet size is 2 kBtyes - Section 9.5.2 (CXP-001-2021)
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def __init__(self, size=16000):
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# double buffer need eop to function correctly
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self.submodules.double_buffer = double_buffer = Double_Stream_Buffer(size)
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self.submodules.parser = parser = Stream_Parser()
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self.submodules.frame_extractor = frame_extractor = Frame_Extractor()
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pipeline = [double_buffer, parser, frame_extractor]
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for s, d in zip(pipeline, pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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self.sink = pipeline[0].sink
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self.source = pipeline[-1].source
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# no backpressure for sim purposes
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self.sync += self.source.ack.eq(1)
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