morgan/artiq-zynq
1
0
Fork 0
forked from M-Labs/artiq-zynq
Code Pull Requests Activity

upconn GW: improve var/fn naming

Browse Source
This commit is contained in:
morgan 2025-01-14 12:17:39 +08:00
parent 3ca9c12c50
commit 7af9cc2d02
1 changed files with 9 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
src/gateware/cxp_upconn.py
View File

@ -9,7 +9,7 @@ from misoc.interconnect.csr import *
from cxp_pipeline import char_layout from cxp_pipeline import char_layout
@ResetInserter() @ResetInserter()
class UpConn_ClockGen(Module): class ClockGen(Module):
def __init__(self, sys_clk_freq): def __init__(self, sys_clk_freq):
self.clk = Signal() self.clk = Signal()
self.clk_10x = Signal() # 20.83MHz 48ns or 41.66MHz 24ns self.clk_10x = Signal() # 20.83MHz 48ns or 41.66MHz 24ns
@ -121,19 +121,19 @@ class Transmitter(Module, AutoCSR):
def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads): def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads):
self.bitrate2x_enable = Signal() self.bitrate2x_enable = Signal()
self.clk_reset = Signal() self.clk_reset = Signal()
self.tx_enable = Signal() self.enable = Signal()
# # # # # #
self.sink = stream.Endpoint(char_layout) self.sink = stream.Endpoint(char_layout)
self.submodules.cg = cg = UpConn_ClockGen(sys_clk_freq) self.submodules.cg = cg = ClockGen(sys_clk_freq)
self.submodules.encoder = encoder = SingleEncoder(True) self.submodules.encoder = encoder = SingleEncoder(True)
self.submodules.debug_buf = debug_buf = Debug_buffer(char_layout) self.submodules.debug_buf = debug_buf = Debug_buffer(char_layout)
oe = Signal() oe = Signal()
self.sync += [ self.sync += [
If(self.tx_enable, If(self.enable,
self.sink.ack.eq(0), self.sink.ack.eq(0),
# DEBUG: # DEBUG:
@ -175,22 +175,22 @@ class Transmitter(Module, AutoCSR):
serdes.oe.eq(oe), serdes.oe.eq(oe),
] ]
class CXP_UpConn_PHYS(Module, AutoCSR): class CXP_TXPHYs(Module, AutoCSR):
def __init__(self, pads, sys_clk_freq, debug_sma, pmod_pads): def __init__(self, pads, sys_clk_freq, debug_sma, pmod_pads):
self.clk_reset = CSR() self.clk_reset = CSR()
self.bitrate2x_enable = CSRStorage() self.bitrate2x_enable = CSRStorage()
self.tx_enable = CSRStorage() self.enable = CSRStorage()
# # # # # #
self.tx_phys = [] self.phys = []
for i, pad in enumerate(pads): for i, pad in enumerate(pads):
tx = Transmitter(pad, sys_clk_freq, debug_sma, pmod_pads) tx = Transmitter(pad, sys_clk_freq, debug_sma, pmod_pads)
self.tx_phys.append(tx) self.phys.append(tx)
setattr(self.submodules, "tx"+str(i), tx) setattr(self.submodules, "tx"+str(i), tx)
self.sync += [ self.sync += [
tx.clk_reset.eq(self.clk_reset.re), tx.clk_reset.eq(self.clk_reset.re),
tx.bitrate2x_enable.eq(self.bitrate2x_enable.storage), tx.bitrate2x_enable.eq(self.bitrate2x_enable.storage),
tx.tx_enable.eq(self.tx_enable.storage), tx.enable.eq(self.enable.storage),
] ]