diff --git a/src/gateware/cxp_upconn.py b/src/gateware/cxp_upconn.py
index 4b0363d..82ddb85 100644
--- a/src/gateware/cxp_upconn.py
+++ b/src/gateware/cxp_upconn.py
@@ -9,7 +9,7 @@ from misoc.interconnect.csr import *
 from cxp_pipeline import char_layout
 
 @ResetInserter()
-class UpConn_ClockGen(Module):
+class ClockGen(Module):
     def __init__(self, sys_clk_freq):
         self.clk = Signal()
         self.clk_10x = Signal() # 20.83MHz 48ns or 41.66MHz 24ns
@@ -121,19 +121,19 @@ class Transmitter(Module, AutoCSR):
     def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads):
         self.bitrate2x_enable = Signal()
         self.clk_reset = Signal()
-        self.tx_enable = Signal()
+        self.enable = Signal()
 
         # # #
 
         self.sink = stream.Endpoint(char_layout)
 
-        self.submodules.cg = cg = UpConn_ClockGen(sys_clk_freq)
+        self.submodules.cg = cg = ClockGen(sys_clk_freq)
         self.submodules.encoder = encoder = SingleEncoder(True)
         self.submodules.debug_buf = debug_buf = Debug_buffer(char_layout)
 
         oe = Signal()
         self.sync += [
-            If(self.tx_enable,
+            If(self.enable,
                 self.sink.ack.eq(0),
 
                 # DEBUG:
@@ -175,22 +175,22 @@ class Transmitter(Module, AutoCSR):
             serdes.oe.eq(oe),
         ]
 
-class CXP_UpConn_PHYS(Module, AutoCSR):
+class CXP_TXPHYs(Module, AutoCSR):
     def __init__(self, pads, sys_clk_freq, debug_sma, pmod_pads):
         self.clk_reset = CSR()
         self.bitrate2x_enable = CSRStorage()
-        self.tx_enable = CSRStorage()
+        self.enable = CSRStorage()
 
         # # #
 
 
-        self.tx_phys = []
+        self.phys = []
         for i, pad in enumerate(pads):
             tx = Transmitter(pad, sys_clk_freq, debug_sma, pmod_pads)
-            self.tx_phys.append(tx)
+            self.phys.append(tx)
             setattr(self.submodules, "tx"+str(i), tx)
             self.sync += [
                 tx.clk_reset.eq(self.clk_reset.re),
                 tx.bitrate2x_enable.eq(self.bitrate2x_enable.storage),
-                tx.tx_enable.eq(self.tx_enable.storage),
+                tx.enable.eq(self.enable.storage),
             ]