morgan
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Pull Requests Activity

proto FW: use memory buffer for tx 

proto FW: restore test packet

proto FW: fix test packet doesn't return mux

proto fw: add loopback tx & restore gtx test

proto fw: add mem size
This commit is contained in:
morgan 2024-09-26 13:23:59 +08:00
parent 007d40dfc3
commit 78200e93d0
1 changed files with 34 additions and 66 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

90
src/libboard_artiq/src/cxp_proto.rs
View File

@ -6,10 +6,12 @@ use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
use io::Cursor;
use libboard_zynq::{println, timer::GlobalTimer};
use crate::{mem::mem::CXP_MEM, pl::csr};
use crate::{mem::mem::{CXP_LOOPBACK_MEM, CXP_MEM},
pl::csr};
const MAX_PACKET: usize = 128;
const DATA_MAXSIZE: usize = /*max size*/MAX_PACKET - /*Tag*/4 - /*Op code & length*/4 - /*addr*/4 - /*CRC*/4 ;
const MEM_SIZE: usize = 0x200;
#[derive(Debug)]
pub enum Error {
@ -119,28 +121,29 @@ pub fn send(packet: &Packet) -> Result<(), Error> {
}
fn send_data_packet(packet: &Packet) -> Result<(), Error> {
let mut buffer: [u8; MAX_PACKET] = [0; MAX_PACKET];
let mut writer = Cursor::new(&mut buffer[..]);
unsafe {
// TODO: put this in mem group
while csr::cxp::upconn_command_tx_read() == 1 {}
let ptr = CXP_MEM[0].base as *mut u32;
let mut writer = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, MEM_SIZE));
packet.write_to(&mut writer)?;
unsafe {
let len = writer.position();
csr::cxp::upconn_command_len_write(len as u8);
for data in writer.get_ref()[..len].iter() {
while csr::cxp::upconn_command_writeable_read() == 0 {}
csr::cxp::upconn_command_data_write(*data);
}
csr::cxp::upconn_command_tx_word_len_write(writer.position() as u8 / 4);
csr::cxp::upconn_command_tx_write(1);
}
Ok(())
}
fn send_test_packet() -> Result<(), Error> {
unsafe {
while csr::cxp::upconn_tx_busy_read() == 1 {}
while csr::cxp::upconn_testseq_tx_read() == 1 {}
csr::cxp::upconn_tx_testmode_en_write(1);
csr::cxp::upconn_testseq_stb_write(1);
while csr::cxp::upconn_testseq_busy_read() == 1 {}
csr::cxp::upconn_testseq_tx_write(1);
// wait till all test packet is out before switching back
while csr::cxp::upconn_testseq_tx_read() == 1 {}
csr::cxp::upconn_tx_testmode_en_write(0);
}
Ok(())
@ -212,20 +215,16 @@ pub fn print_packetu32(pak: &[u32], k: &[u8]) {
}
pub fn downconn_debug_send(packet: &Packet) -> Result<(), Error> {
let mut buffer: [u8; MAX_PACKET] = [0; MAX_PACKET];
let mut writer = Cursor::new(&mut buffer[..]);
unsafe {
// TODO: put this in mem group
while csr::cxp::downconn_command_tx_read() == 1 {}
let ptr = CXP_LOOPBACK_MEM[0].base as *mut u32;
let mut writer = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, MEM_SIZE));
packet.write_to(&mut writer)?;
unsafe {
csr::cxp::downconn_mux_sel_write(0);
let len = writer.position();
csr::cxp::downconn_debug_src_len_write(len as u8);
for data in writer.get_ref()[..len].iter() {
while csr::cxp::downconn_debug_src_writeable_read() == 0 {}
csr::cxp::upconn_command_data_write(*data);
csr::cxp::downconn_debug_src_data_write(*data);
}
csr::cxp::downconn_command_tx_word_len_write(writer.position() as u8 / 4);
csr::cxp::downconn_command_tx_write(1);
}
Ok(())
@ -233,49 +232,18 @@ pub fn downconn_debug_send(packet: &Packet) -> Result<(), Error> {
pub fn downconn_debug_send_trig_ack() {
unsafe {
csr::cxp::downconn_mux_sel_write(1);
csr::cxp::downconn_ack_write(1);
}
}
pub fn downconn_send_test_packet() {
unsafe {
csr::cxp::downconn_mux_sel_write(2);
csr::cxp::downconn_testseq_stb_write(1);
while csr::cxp::downconn_testseq_busy_read() == 1 {}
}
}
while csr::cxp::downconn_testseq_tx_read() == 1 {}
csr::cxp::downconn_mux_sel_write(1);
csr::cxp::downconn_testseq_tx_write(1);
pub fn ram_writer_send(packet: &Packet) -> Result<(), Error> {
unsafe {
// TODO: put this in mem group
while csr::cxp::transmitter_cxp_tx_read() == 1 {}
let ptr = CXP_MEM[0].base as *mut u32;
let mut writer = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, 0x200 as usize));
packet.write_to(&mut writer)?;
csr::cxp::transmitter_cxp_tx_word_len_write(writer.position() as u8 / 4);
csr::cxp::transmitter_cxp_tx_write(1);
while csr::cxp::transmitter_cxp_tx_read() == 1 {}
// read the fifo
const LEN: usize = 10;
let mut pak_arr: [u32; LEN] = [0; LEN];
let mut k_arr: [u8; LEN] = [0; LEN];
let mut i: usize = 0;
while csr::cxp::transmitter_debug_out_dout_valid_read() == 1 {
pak_arr[i] = csr::cxp::transmitter_debug_out_dout_pak_read();
k_arr[i] = csr::cxp::transmitter_debug_out_kout_pak_read();
// println!("received {:#04X}", pak_arr[i]);
csr::cxp::transmitter_debug_out_inc_write(1);
i += 1;
if i == LEN {
break;
// wait till all test packet is out before switching back
while csr::cxp::downconn_testseq_tx_read() == 1 {}
csr::cxp::downconn_mux_sel_write(0);
}
}
print_packetu32(&pak_arr, &k_arr);
}
Ok(())
}