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downocnn fw: update csr

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morgan 2025-01-14 14:22:27 +08:00
parent a731b23e03
commit 77d3ef6da0
1 changed files with 18 additions and 18 deletions
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36
src/libboard_artiq/src/cxp_downconn.rs
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@ -13,21 +13,21 @@ pub fn loopback_testing(channel: usize, timer: &mut GlobalTimer, speed: cxp_phys
timer.delay_us(50_000);
info!(
"tx_phaligndone = {} | rx_phaligndone = {}",
(CXP[channel].downconn_txinit_phaligndone_read)(),
(CXP[channel].downconn_rxinit_phaligndone_read)(),
(CXP[channel].rx_txinit_phaligndone_read)(),
(CXP[channel].rx_rxinit_phaligndone_read)(),
);
// enable txdata tranmission thought MGTXTXP, required by PMA loopback
// (CXP[channel].downconn_txenable_write)(1);
// (CXP[channel].rx_txenable_write)(1);
info!("waiting for rx to align...");
while (CXP[channel].downconn_rx_ready_read)() != 1 {}
while (CXP[channel].rx_ready_read)() != 1 {}
info!("rx ready!");
// cxp_proto::downconn_send_test_packet(channel);
// cxp_proto::rx_send_test_packet(channel);
// FIXME: why test + trig ack doesn't work well for rx??
// cxp_proto::downconn_debug_send_trig_ack(channel);
// cxp_proto::rx_debug_send_trig_ack(channel);
// const DATA_MAXSIZE: usize = 253;
// let data_size = 4; // no. of bytes
@ -35,7 +35,7 @@ pub fn loopback_testing(channel: usize, timer: &mut GlobalTimer, speed: cxp_phys
// let data: u32 = 0xDADA as u32;
// let mut data_slice: [u8; DATA_MAXSIZE] = [0; DATA_MAXSIZE];
// data_slice[..4].clone_from_slice(&data.to_be_bytes());
// cxp_proto::downconn_debug_send(
// cxp_proto::rx_debug_send(
// channel,
// &cxp_proto::UpConnPacket::Event {
// conn_id: 0x1234_5678_u32,
@ -52,38 +52,38 @@ pub fn loopback_testing(channel: usize, timer: &mut GlobalTimer, speed: cxp_phys
// timer.delay_us(1000); // wait packet has arrive at RX async fifo
// if (CXP[channel].downconn_trigger_ack_read)() == 1 {
// (CXP[channel].downconn_trigger_ack_write)(1);
// if (CXP[channel].rx_trigger_ack_read)() == 1 {
// (CXP[channel].rx_trigger_ack_write)(1);
// info!("trig ack and cleared");
// }
// if (CXP[channel].downconn_bootstrap_decoder_err_read)() == 1 {
// if (CXP[channel].rx_bootstrap_decoder_err_read)() == 1 {
// info!("!!!!!!!DECODER ERROR!!!!!!! and cleared");
// (CXP[channel].downconn_bootstrap_decoder_err_write)(1);
// (CXP[channel].rx_bootstrap_decoder_err_write)(1);
// }
// info!("packet type = {:#06X}", (CXP[channel].downconn_packet_type_read)());
// info!("packet type = {:#06X}", (CXP[channel].rx_packet_type_read)());
// // cxp_proto::receive(channel as u8).expect("loopback gtx rx error");
// // cxp_proto::downconn_debug_mem_print(channel);
// // cxp_proto::rx_debug_mem_print(channel);
// // DEBUG: print loopback packets
// const LEN: usize = 20;
// let mut pak_arr: [u32; LEN] = [0; LEN];
// let mut k_arr: [u8; LEN] = [0; LEN];
// let mut i: usize = 0;
// while (CXP[channel].downconn_debug_out_dout_valid_read)() == 1 {
// pak_arr[i] = (CXP[channel].downconn_debug_out_dout_pak_read)();
// k_arr[i] = (CXP[channel].downconn_debug_out_kout_pak_read)();
// while (CXP[channel].rx_debug_out_dout_valid_read)() == 1 {
// pak_arr[i] = (CXP[channel].rx_debug_out_dout_pak_read)();
// k_arr[i] = (CXP[channel].rx_debug_out_kout_pak_read)();
// // println!("received {:#04X}", pak_arr[i]);
// (CXP[channel].downconn_debug_out_inc_write)(1);
// (CXP[channel].rx_debug_out_inc_write)(1);
// i += 1;
// if i == LEN {
// break;
// }
// }
// info!("rx ready = {}", (CXP[channel].downconn_rx_ready_read)());
// info!("rx ready = {}", (CXP[channel].rx_rx_ready_read)());
// // cxp_proto::print_packetu32(&pak_arr, &k_arr);
}
}