From 77bff39212f70545244db9fe75033a122ed87d8a Mon Sep 17 00:00:00 2001
From: morgan <mc@m-labs.hk>
Date: Fri, 2 Aug 2024 12:36:27 +0800
Subject: [PATCH] cxp downconn fw: add manual alignment test

---
 src/libboard_artiq/src/cxp_downconn.rs | 64 ++++++++++++++------------
 1 file changed, 35 insertions(+), 29 deletions(-)

diff --git a/src/libboard_artiq/src/cxp_downconn.rs b/src/libboard_artiq/src/cxp_downconn.rs
index d44020f..14fef1c 100644
--- a/src/libboard_artiq/src/cxp_downconn.rs
+++ b/src/libboard_artiq/src/cxp_downconn.rs
@@ -39,8 +39,8 @@ fn loopback_testing(timer: &mut GlobalTimer, data: u8, control_bit: u8) {
         // 312.5MHz
         const LEN: usize = 4;
         const DATA: [[u8; LEN]; 2] = [
-            // [K28_5, K28_5, K28_5, K28_1, K28_5, K28_5, K28_5, K28_5],
-            // [1, 1, 1, 1, 1, 1, 1, 1],
+            // [K28_5, K28_1, K28_5, K28_1],
+            // [1, 1, 1, 1],
             [K28_5, K28_1, K28_1, D21_5],
             [1, 1, 1, 0],
         ];
@@ -79,39 +79,46 @@ fn loopback_testing(timer: &mut GlobalTimer, data: u8, control_bit: u8) {
         csr::cxp::downconn_txenable_write(1);
 
         info!("waiting for rx to align...");
-        while csr::cxp::downconn_rx_ready_read() != 1 {}
         timer.delay_us(50_000);
-        info!("rx ready!");
+        // while csr::cxp::downconn_rx_ready_read() != 1 {}
+        // info!("rx ready!");
 
         // csr::cxp::data_3_write(data);
         // csr::cxp::control_bit_3_write(control_bit);
-        println!(
-            "data[0] = {:#04x} control bit = {:#b} encoded = {:#012b}",
-            csr::cxp::downconn_data_0_read(),
-            csr::cxp::downconn_control_bit_0_read(),
-            csr::cxp::downconn_encoded_0_read(),
-        );
-        println!(
-            "data[1] = {:#04x} control bit = {:#b} encoded = {:#012b}",
-            csr::cxp::downconn_data_1_read(),
-            csr::cxp::downconn_control_bit_1_read(),
-            csr::cxp::downconn_encoded_1_read(),
-        );
+        // println!(
+        //     "data[0] = {:#04x} control bit = {:#b} encoded = {:#012b}",
+        //     csr::cxp::downconn_data_0_read(),
+        //     csr::cxp::downconn_control_bit_0_read(),
+        //     csr::cxp::downconn_encoded_0_read(),
+        // );
+        // println!(
+        //     "data[1] = {:#04x} control bit = {:#b} encoded = {:#012b}",
+        //     csr::cxp::downconn_data_1_read(),
+        //     csr::cxp::downconn_control_bit_1_read(),
+        //     csr::cxp::downconn_encoded_1_read(),
+        // );
 
-        for _ in 0..20 {
-            timer.delay_us(100);
+        // for _ in 0..20 {
+        loop {
+            // timer.delay_us(100);
+            println!(
+                "data = {:#022b} | rx ready = {}",
+                (csr::cxp::downconn_rxdata_0_read() as u32 | ((csr::cxp::downconn_rxdata_1_read() as u32) << 10)),
+                csr::cxp::downconn_rx_ready_read()
+            );
+            timer.delay_us(1_000_000);
             // println!(
             //     "data[0] = {:#012b} data[1] = {:#012b}",
             //     csr::cxp::rxdata_0_read(),
             //     csr::cxp::rxdata_1_read(),
             // );
-            println!(
-                "decoded_data[0] = {:#04x} decoded_k[0] = {:#b} decoded_data[1] = {:#04x} decoded_k[1] = {:#b}",
-                csr::cxp::downconn_decoded_data_0_read(),
-                csr::cxp::downconn_decoded_k_0_read(),
-                csr::cxp::downconn_decoded_data_1_read(),
-                csr::cxp::downconn_decoded_k_1_read(),
-            );
+            // println!(
+            //     "decoded_data[0] = {:#04x} decoded_k[0] = {:#b} decoded_data[1] = {:#04x} decoded_k[1] = {:#b}",
+            //     csr::cxp::downconn_decoded_data_0_read(),
+            //     csr::cxp::downconn_decoded_k_0_read(),
+            //     csr::cxp::downconn_decoded_data_1_read(),
+            //     csr::cxp::downconn_decoded_k_1_read(),
+            // );
         }
     }
 }
@@ -152,7 +159,7 @@ pub fn change_linerate(timer: &mut GlobalTimer, speed: CXP_SPEED) {
     let settings = txusrclk::get_txusrclk_config(speed);
     txusrclk::setup(timer, settings);
 
-    // TODO: set TX/RX DIVIDER via TX/RXRATE
+    // TODO: set QPLL_FBDIV via DRP
     change_qpll_settings(speed);
 
     unsafe {
@@ -162,10 +169,9 @@ pub fn change_linerate(timer: &mut GlobalTimer, speed: CXP_SPEED) {
         info!("QPLL locked");
     }
 
-    // reset tx&rx for phase alignment
     unsafe {
-        csr::cxp::downconn_tx_restart_write(1); // <--- NOTE: changing TXRATE will do reset automatically, no need to manually reset
-        csr::cxp::downconn_rx_restart_write(1); // <--- NOTE: this doesn't do anything atm
+        csr::cxp::downconn_tx_restart_write(1);
+        csr::cxp::downconn_rx_restart_write(1);
     }
 }