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cxp: add packet end inserter

This commit is contained in:
morgan 2024-08-30 13:33:35 +08:00
parent 029d3b8776
commit 770d0b159a
1 changed files with 3 additions and 4 deletions
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7
src/gateware/cxp.py
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@ -95,15 +95,14 @@ class CXP_TX_Core(Module, AutoCSR):
len = Signal(6, reset=1)
# TODO: add end of packet (eop) interface for firmware and try out crc_inserters
# a buf is used to simulated a proper endpoint which hold source.stb high as long as data is available
# otherwise, CSR.re only hold when CSR is written to and it cannot act as a proper source
self.submodules.buf_in = buf_in = stream.SyncFIFO(cxp_phy_layout(), 2)
self.submodules.buf_out = buf_out = stream.SyncFIFO(cxp_phy_layout(), 64)
self.submodules.pak_start = pak_start = Packet_Start_Inserter(cxp_phy_layout())
self.submodules.crc_inserter = crc_inserters = CXPCRC32Inserter(cxp_phy_layout())
self.submodules.pak_start = pak_start = Packet_Start_Inserter(cxp_phy_layout())
self.submodules.pak_end = pak_end = Packet_End_Inserter(cxp_phy_layout())
self.sync += [
# input
@ -130,7 +129,7 @@ class CXP_TX_Core(Module, AutoCSR):
]
tx_pipeline = [ buf_in, crc_inserters, pak_start, buf_out]
tx_pipeline = [ buf_in, crc_inserters, pak_start, pak_end, buf_out]
for s, d in zip(tx_pipeline, tx_pipeline[1:]):
self.comb += s.source.connect(d.sink)