cxp: add upconn, downconn & crc

cxp: add crc32 for cxp
cxp: add upconn & downconn

src/gateware/cxp.py

@@ -0,0 +1,74 @@
+from migen import *
+from misoc.interconnect.csr import *
+from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine
+
+from cxp_downconn import CXP_DownConn
+from cxp_upconn import CXP_UpConn
+
+class CXP(Module, AutoCSR):
+    def __init__(self, refclk, pads, sys_clk_freq, debug_sma, pmod_pads):
+        self.submodules.crc = CXP_CRC(8)
+        # FIFOs with transmission priority
+        # 0: Trigger packet
+        # 1: IO acknowledgment for trigger packet
+        # 2: All other packets
+        self.submodules.upconn = CXP_UpConn(debug_sma, sys_clk_freq, pmod_pads)
+
+        self.submodules.downconn = CXP_DownConn(refclk, pads, sys_clk_freq, debug_sma, pmod_pads)
+
+
+class CXP_CRC(Module, AutoCSR):
+    width = 32
+    polynom = 0x04C11DB7
+    seed = 2**width-1
+    def __init__(self, data_width):
+        self.d = Signal(data_width)
+        self.stb = Signal()
+        self.reset = Signal()
+        self.val = Signal(self.width, reset=self.seed)
+
+        self.data = CSR(data_width)
+        self.en = CSR()
+        self.value = CSRStatus(self.width)
+        self.processed = CSRStatus(self.width)
+
+        # # #
+        
+        self.submodules.engine = LiteEthMACCRCEngine(data_width, self.width, self.polynom)
+
+        self.sync += [
+            self.val.eq(self.engine.next),
+            If(self.stb,
+                self.engine.data.eq(self.d), 
+
+                If(self.reset,
+                    self.engine.last.eq(self.seed), 
+                    # clear reset bit
+                    self.reset.eq(0),
+                ).Else(
+                    self.engine.last.eq(self.val), 
+                )
+            ),
+        ]
+
+        # DEBUG: remove those csr
+        # TODO: do char bit reverse outside of this submodule
+
+        p0 = Signal(8)
+        p1 = Signal(8)
+        p2 = Signal(8)
+        p3 = Signal(8)
+        self.comb += [
+            p3.eq(self.engine.next[:8][::-1]),
+            p2.eq(self.engine.next[8:16][::-1]),
+            p1.eq(self.engine.next[16:24][::-1]),
+            p0.eq(self.engine.next[24:32][::-1]),
+        ]
+        self.sync += [
+            self.d.eq(self.data.r),
+            self.stb.eq(self.data.re),
+            If(self.en.re, self.reset.eq(1)),
+
+            self.value.status.eq(self.engine.next),
+            self.processed.status.eq(Cat(p3, p2, p1, p0)),
+        ]