diff --git a/src/gateware/cxp_downconn.py b/src/gateware/cxp_downconn.py
index 4631f1c..11e015d 100644
--- a/src/gateware/cxp_downconn.py
+++ b/src/gateware/cxp_downconn.py
@@ -54,8 +54,6 @@ class CXP_DownConn(Module, AutoCSR):
         # GTPTXPhaseAlignement for inspiration
 
         # Connect all GTX connections' DRP
-        self.tx_div = CSRStorage(3)
-        self.rx_div = CSRStorage(3)
 
         self.gtx_daddr = CSRStorage(9)
         self.gtx_dread = CSR()
@@ -80,8 +78,6 @@ class CXP_DownConn(Module, AutoCSR):
 
             self.comb += gtx.dclk.eq(ClockSignal("sys"))
             self.sync += [
-                gtx.tx_rate.eq(self.tx_div.storage),
-                gtx.rx_rate.eq(self.rx_div.storage),
 
                 gtx.den.eq(0),
                 gtx.dwen.eq(0),
@@ -468,9 +464,6 @@ class GTX(Module):
         self.txenable = Signal()
         self.rx_ready = Signal()
 
-        self.tx_rate = Signal(3)
-        self.rx_rate = Signal(3)
-
         # Dynamic Reconfiguration Ports
         self.daddr = Signal(9)
         self.dclk = Signal()
@@ -531,10 +524,6 @@ class GTX(Module):
                 p_PD_TRANS_TIME_TO_P2=0x64,
                 i_CPLLPD=1,
 
-                # Dynamic Tx/Rx divider
-                i_TXRATE=self.tx_rate,
-                i_RXRATE=self.rx_rate,
-
                 # QPLL
                 i_QPLLCLK=qpll.clk,
                 i_QPLLREFCLK=qpll.refclk,