forked from M-Labs/artiq-zynq
cxp upconn fw: rename csr
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2e984ab48e
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730480aaa8
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@ -46,23 +46,23 @@ pub fn pipeline_test(timer: &mut GlobalTimer) {
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unsafe {
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unsafe {
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// eop = 1 (End of packet) at the last data input
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// eop = 1 (End of packet) at the last data input
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csr::cxp::txcore_din_len_write(arr.len() as u8);
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csr::cxp::upconn_tx_command_din_len_write(arr.len() as u8);
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csr::cxp::txcore_packet_type_write(0x02); // read control command
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csr::cxp::upconn_tx_command_packet_type_write(0x02); // read control command
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for a in arr.iter() {
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for a in arr.iter() {
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while csr::cxp::txcore_din_ready_read() == 0 {}
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while csr::cxp::upconn_tx_command_din_ready_read() == 0 {}
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// println!("{:#04X}", *a);
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// println!("{:#04X}", *a);
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csr::cxp::txcore_din_pak_write(*a);
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csr::cxp::upconn_tx_command_din_data_write(*a);
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}
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}
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// wait for pipelining
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// wait for pipelining
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timer.delay_us(1);
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timer.delay_us(1);
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let mut i: usize = 0;
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let mut i: usize = 0;
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while csr::cxp::txcore_dout_valid_read() == 1 {
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while csr::cxp::upconn_dout_valid_read() == 1 {
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pak_arr[i] = csr::cxp::txcore_dout_pak_read();
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pak_arr[i] = csr::cxp::upconn_dout_pak_read();
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// println!("received {:#04X}", pak_arr[i]);
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// println!("received {:#04X}", pak_arr[i]);
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csr::cxp::txcore_inc_write(1);
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csr::cxp::upconn_inc_write(1);
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i += 1;
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i += 1;
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}
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}
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