From 730480aaa8365034b6d1b5c595ef5938427dfc50 Mon Sep 17 00:00:00 2001 From: morgan Date: Mon, 2 Sep 2024 16:50:12 +0800 Subject: [PATCH] cxp upconn fw: rename csr --- src/libboard_artiq/src/cxp_upconn.rs | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/libboard_artiq/src/cxp_upconn.rs b/src/libboard_artiq/src/cxp_upconn.rs index ca34648..094a672 100644 --- a/src/libboard_artiq/src/cxp_upconn.rs +++ b/src/libboard_artiq/src/cxp_upconn.rs @@ -46,23 +46,23 @@ pub fn pipeline_test(timer: &mut GlobalTimer) { unsafe { // eop = 1 (End of packet) at the last data input - csr::cxp::txcore_din_len_write(arr.len() as u8); - csr::cxp::txcore_packet_type_write(0x02); // read control command + csr::cxp::upconn_tx_command_din_len_write(arr.len() as u8); + csr::cxp::upconn_tx_command_packet_type_write(0x02); // read control command for a in arr.iter() { - while csr::cxp::txcore_din_ready_read() == 0 {} + while csr::cxp::upconn_tx_command_din_ready_read() == 0 {} // println!("{:#04X}", *a); - csr::cxp::txcore_din_pak_write(*a); + csr::cxp::upconn_tx_command_din_data_write(*a); } // wait for pipelining timer.delay_us(1); let mut i: usize = 0; - while csr::cxp::txcore_dout_valid_read() == 1 { - pak_arr[i] = csr::cxp::txcore_dout_pak_read(); + while csr::cxp::upconn_dout_valid_read() == 1 { + pak_arr[i] = csr::cxp::upconn_dout_pak_read(); // println!("received {:#04X}", pak_arr[i]); - csr::cxp::txcore_inc_write(1); + csr::cxp::upconn_inc_write(1); i += 1; }