diff --git a/src/gateware/cxp_pipeline.py b/src/gateware/cxp_pipeline.py
index 54560f7..d11c829 100644
--- a/src/gateware/cxp_pipeline.py
+++ b/src/gateware/cxp_pipeline.py
@@ -1,7 +1,7 @@
 from migen import *
 from misoc.interconnect.csr import *
 from misoc.interconnect import stream
-from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine, LiteEthMACCRCInserter, LiteEthMACCRC32Inserter
+from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine, LiteEthMACCRCInserter 
 
 class Code_Inserter(Module):
     """Code inserter
@@ -76,4 +76,50 @@ class Code_Inserter(Module):
             
         )
 
+@ResetInserter()
+@CEInserter()
+class CXPCRC32(Module):
+    """CoaXPress CRC
 
+    Implement an CoaXPress CRC generator/checker.
+
+    Parameters
+    ----------
+    data_width : int
+        Width of the data bus.
+
+    Attributes
+    ----------
+    d : in
+        Data input.
+    value : out
+        CRC value (used for generator).
+    error : out
+        CRC error (used for checker).
+    """
+    # Section 9.2.2.2 (CXP-001-2021)
+    width = 32
+    polynom = 0x04C11DB7
+    seed = 2**width-1
+    check = 0x00000000
+    def __init__(self, data_width):
+        self.data = Signal(data_width)
+        self.value = Signal(self.width)
+        self.error = Signal()
+
+        # # #
+
+        self.submodules.engine = LiteEthMACCRCEngine(data_width, self.width, self.polynom)
+        reg = Signal(self.width, reset=self.seed)
+        self.sync += reg.eq(self.engine.next)
+        self.comb += [
+            self.engine.data.eq(self.data),
+            self.engine.last.eq(reg),
+
+            self.value.eq(reg[::-1]),
+            self.error.eq(self.engine.next != self.check)
+        ]
+
+class CXPCRC32Inserter(LiteEthMACCRCInserter):
+    def __init__(self, layout):
+        LiteEthMACCRCInserter.__init__(self, CXPCRC32, layout)