forked from M-Labs/artiq-zynq
parent
5eadc9b49e
commit
6e98d8952a
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@ -300,16 +300,14 @@ class RX_Debug_Buffer(Module,AutoCSR):
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@FullMemoryWE()
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class CXP_Data_Packet_Decode(Module):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout)
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# This is where data stream comes out
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self.source = stream.Endpoint(word_layout)
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self.packet_type = Signal(8)
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self.decode_err = Signal()
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self.packet_type_rx = Signal(8)
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self.decode_err_rx = Signal()
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self.test_err_rx = Signal()
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self.test_err = Signal()
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# # #
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# DEBUG: remove debug
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# TODO: decode all packet type here
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# TODO: data&event -> memory
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# TODO: heartbeat
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type = {
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@ -323,6 +321,9 @@ class CXP_Data_Packet_Decode(Module):
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"debug" : 0x02,
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}
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self.sink = stream.Endpoint(word_layout)
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self.source = stream.Endpoint(word_layout)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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@ -333,14 +334,11 @@ class CXP_Data_Packet_Decode(Module):
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)
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)
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# TODO: decode all packet type here
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cnt = Signal(max=0x100)
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fsm.act("DECODE",
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self.sink.ack.eq(1),
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If(self.sink.stb,
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NextValue(self.packet_type_rx, self.sink.data[:8]),
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NextValue(self.packet_type, self.sink.data[:8]),
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Case(self.sink.data[:8],{
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type["data_stream"]: NextState("STREAMING"),
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@ -354,7 +352,7 @@ class CXP_Data_Packet_Decode(Module):
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type["debug"]: NextState("LOAD_BUFFER"),
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"default": [
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self.decode_err_rx.eq(1),
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self.decode_err.eq(1),
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# wait till next valid packet
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NextState("IDLE"),
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],
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@ -372,7 +370,7 @@ class CXP_Data_Packet_Decode(Module):
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NextState("IDLE"),
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).Else(
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If(((self.sink.data != Cat(cnt, cnt+1, cnt+2, cnt+3))),
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self.test_err_rx.eq(1),
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self.test_err.eq(1),
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),
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If(cnt == 0xFC,
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NextValue(cnt, cnt.reset),
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