forked from M-Labs/artiq-zynq
zc706: fix debug sma pad
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parent
dd36c01c13
commit
6e7bc912c9
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@ -683,6 +683,7 @@ class CXP_FMC():
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platform.add_extension(debug_sma)
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platform.add_extension(debug_sma)
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platform.add_extension(pmod1_33)
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platform.add_extension(pmod1_33)
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debug_sma_pad = platform.request("user_sma_clock_33")
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pmod_pads = [platform.request("pmod1_33", i) for i in range(8)]
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pmod_pads = [platform.request("pmod1_33", i) for i in range(8)]
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clk_freq = 125e6
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clk_freq = 125e6
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@ -697,7 +698,7 @@ class CXP_FMC():
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upconn_pads=cxp_upconn_pads,
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upconn_pads=cxp_upconn_pads,
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downconn_pads=cxp_downconn_pads,
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downconn_pads=cxp_downconn_pads,
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sys_clk_freq=clk_freq,
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sys_clk_freq=clk_freq,
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debug_sma=platform.request("user_sma_clock_33"),
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debug_sma=debug_sma_pad,
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pmod_pads = pmod_pads
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pmod_pads = pmod_pads
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)
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)
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self.csr_devices.append("cxp_phys")
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self.csr_devices.append("cxp_phys")
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@ -712,7 +713,7 @@ class CXP_FMC():
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# TODO: cdr = ClockDomainsRenamer({"cxp_gtx_rx": "cxp_gtx_rx" + str(i)})
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# TODO: cdr = ClockDomainsRenamer({"cxp_gtx_rx": "cxp_gtx_rx" + str(i)})
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cxp_interface = cxp.CXP_Interface(tx, rx, debug_sma, pmod_pads)
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cxp_interface = cxp.CXP_Interface(tx, rx, debug_sma_pad, pmod_pads)
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setattr(self.submodules, cxp_name, cxp_interface )
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setattr(self.submodules, cxp_name, cxp_interface )
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self.csr_devices.append(cxp_name)
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self.csr_devices.append(cxp_name)
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cxp_csr_group.append(cxp_name)
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cxp_csr_group.append(cxp_name)
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