From 6e4ae2e1d188a65d8cdbcc8a316f44ea74c3e361 Mon Sep 17 00:00:00 2001
From: morgan <mc@m-labs.hk>
Date: Tue, 13 Aug 2024 11:58:29 +0800
Subject: [PATCH] cxp downconn: add qpll drp

---
 src/gateware/cxp_downconn.py | 70 ++++++++++++++++++++++++++++++------
 1 file changed, 60 insertions(+), 10 deletions(-)

diff --git a/src/gateware/cxp_downconn.py b/src/gateware/cxp_downconn.py
index 9f71685..bdd12e7 100644
--- a/src/gateware/cxp_downconn.py
+++ b/src/gateware/cxp_downconn.py
@@ -67,7 +67,7 @@ class CXP_DownConn(Module, AutoCSR):
         self.gtx_dout = CSRStatus(16)
         self.gtx_dready = CSR()
 
-        self.comb += gtx.dclk.eq(ClockSignal("sys")),
+        self.comb += gtx.dclk.eq(ClockSignal("sys"))
         self.sync += [
             gtx.tx_rate.eq(self.tx_div.storage),
             gtx.rx_rate.eq(self.rx_div.storage),
@@ -92,7 +92,38 @@ class CXP_DownConn(Module, AutoCSR):
             ),
         ]
 
+        # QPLL DRP
 
+        self.qpll_daddr = CSRStorage(8)
+        self.qpll_dread = CSR()
+        self.qpll_din_stb = CSR()
+        self.qpll_din = CSRStorage(16)
+
+        self.qpll_dout = CSRStatus(16)
+        self.qpll_dready = CSR()
+
+        self.comb += qpll.dclk.eq(ClockSignal("sys"))
+        self.sync += [
+            qpll.den.eq(0),
+            qpll.dwen.eq(0),
+
+            If(self.qpll_dread.re,
+                qpll.den.eq(1),
+                qpll.daddr.eq(self.qpll_daddr.storage),
+            ).Elif(self.qpll_din_stb.re,
+                qpll.den.eq(1),
+                qpll.dwen.eq(1),
+                qpll.daddr.eq(self.qpll_daddr.storage),
+                qpll.din.eq(self.qpll_din.storage),
+            ),
+            If(qpll.dready,
+               self.qpll_dready.w.eq(1),
+               self.qpll_dout.status.eq(qpll.dout),
+            ),
+            If(self.qpll_dready.re,
+               self.qpll_dready.w.eq(0),
+            ),
+        ]
 
         # DEBUG: txusrclk PLL DRG
         
@@ -158,8 +189,8 @@ class CXP_DownConn(Module, AutoCSR):
             Instance("OBUF", i_I=gtx.comma_det.restart, o_O=pmod_pads[2]),
             Instance("OBUF", i_I=aligned, o_O=pmod_pads[3]),
             Instance("OBUF", i_I=gtx.comma_det.ready, o_O=pmod_pads[4]),
-            Instance("OBUF", i_I=valid_data, o_O=pmod_pads[5]),
-            # Instance("OBUF", i_I=, o_O=pmod_pads[6]),
+            Instance("OBUF", i_I=gtx.comma_det.check_ps.o, o_O=pmod_pads[5]),
+            Instance("OBUF", i_I=valid_data, o_O=pmod_pads[6]),
             # Instance("OBUF", i_I=, o_O=pmod_pads[7]),
 
             # Instance("OBUF", i_I=gtx.dclk, o_O=pmod_pads[0]),
@@ -189,9 +220,6 @@ class CXP_DownConn(Module, AutoCSR):
         self.decoded_data_1 = CSRStatus(8)
         self.decoded_k_0 = CSRStatus()
         self.decoded_k_1 = CSRStatus()
-
-        self.shifted = CSRStatus(9)
-
         
         self.sync.cxp_gtx_tx += [
             If(counter == 0,
@@ -219,9 +247,6 @@ class CXP_DownConn(Module, AutoCSR):
             self.rxdata_1.status.eq(self.gtx.decoders[1].input),
             self.decoded_data_1.status.eq(self.gtx.decoders[1].d),
             self.decoded_k_1.status.eq(self.gtx.decoders[1].k),
-            # If(self.gtx.clk_aligner.comma_det.detected,
-            #     self.shifted.status.eq(self.gtx.clk_aligner.comma_det.bitshift),
-            # )
         ]
 
 
@@ -242,18 +267,34 @@ class QPLL(Module):
         self.lock = Signal()
         self.reset = Signal()
 
+        # Dynamic Reconfiguration Ports
+        self.daddr = Signal(8)
+        self.dclk = Signal()
+        self.den = Signal()
+        self.dwen = Signal()
+        self.din = Signal(16)
+
+        self.dout = Signal(16)
+        self.dready = Signal()
         # # #
 
         # WARNING: VCO cannot do 12.5GHz on ZC706
         # VCO freq = sys*qpll_fbdiv
         # PLL output = VCO/2
-        qpll_fbdiv = 0b0100100000
+        qpll_fbdiv = 0b0100100000 # 80 div
         qpll_fbdiv_ratio = 1
 
         fbdiv_real = 80
         refclk_div = 1
         self.Xxout_div = 8
 
+        # qpll_fbdiv = 0b0101110000 # 100 div
+        # qpll_fbdiv_ratio = 1
+
+        # fbdiv_real = 100
+        # refclk_div = 2
+        # self.Xxout_div = 2
+
         self.tx_usrclk_freq = (sys_clk_freq*fbdiv_real/self.Xxout_div)/20
         
         # QPLL reset
@@ -314,6 +355,15 @@ class QPLL(Module):
                 i_RCALENB=0b1,
                 i_QPLLRSVD1=0b0,
                 i_QPLLRSVD2=0b11111,
+
+                # Dynamic Reconfiguration Ports
+                i_DRPADDR=self.daddr,
+                i_DRPCLK=self.dclk,
+                i_DRPEN=self.den,
+                i_DRPWE=self.dwen,
+                i_DRPDI=self.din,
+                o_DRPDO=self.dout,
+                o_DRPRDY=self.dready,
             )
         ]