From 6e27c371ec22cea8688fb258963bf28657b2cb6a Mon Sep 17 00:00:00 2001
From: morgan <mc@m-labs.hk>
Date: Thu, 29 Aug 2024 17:39:07 +0800
Subject: [PATCH] cxp pipeline: code inserter proto

---
 src/gateware/cxp_pipeline.py | 79 ++++++++++++++++++++++++++++++++++++
 1 file changed, 79 insertions(+)
 create mode 100644 src/gateware/cxp_pipeline.py

diff --git a/src/gateware/cxp_pipeline.py b/src/gateware/cxp_pipeline.py
new file mode 100644
index 0000000..54560f7
--- /dev/null
+++ b/src/gateware/cxp_pipeline.py
@@ -0,0 +1,79 @@
+from migen import *
+from misoc.interconnect.csr import *
+from misoc.interconnect import stream
+from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine, LiteEthMACCRCInserter, LiteEthMACCRC32Inserter
+
+class Code_Inserter(Module):
+    """Code inserter
+
+    Inserts data in the front or end of each packet.
+
+    Attributes
+    ----------
+    sink : in
+        Packet octets.
+    source : out
+        Preamble, SFD, and packet octets.
+    """
+
+    def __init__(self, data, k, cxp_phy_layout, insert_infront=True, counts=4):
+        self.sink = sink = stream.Endpoint(cxp_phy_layout)
+        self.source = source = stream.Endpoint(cxp_phy_layout)
+
+        # # #
+
+        cnt = Signal(max=counts)
+        clr_cnt = Signal()
+        inc_cnt = Signal()
+
+        self.sync += [
+            If(clr_cnt,
+                cnt.eq(0),
+            ).Elif(inc_cnt,
+                cnt.eq(cnt + 1),
+            )
+        ]
+
+        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+
+        fsm.act("IDLE",
+            sink.ack.eq(1), # = writable/not full
+            clr_cnt.eq(1),
+            If(sink.stb, # = data input
+                sink.ack.eq(0), # = full
+                NextState("INSERT"),
+            )
+        )
+
+        if insert_infront:
+            fsm.act("INSERT",
+                source.stb.eq(1), # = writing data now
+                source.data.eq(data),
+                source.k.eq(k),
+                If(cnt == counts - 1,
+                    If(source.ack, NextState("COPY"))
+                ).Else(
+                    inc_cnt.eq(source.ack)# = inc_counter only when next pipeline is ready to accept new data
+                )
+            )
+        else:
+            pass
+
+
+        # NOTE: why??
+        self.comb += [
+            source.data.eq(sink.data),
+            source.k.eq(sink.k),
+        ]
+        
+        fsm.act("COPY",
+            sink.connect(source, omit={"data", "k"}),
+
+            # eop = end of packet?
+            If(sink.stb & sink.eop & source.ack,
+                NextState("IDLE"),
+            )
+            
+        )
+
+