forked from M-Labs/artiq-zynq
cxp: update txfifo sink port
This commit is contained in:
parent
2346848541
commit
6d00f52638
|
@ -48,18 +48,18 @@ class UpConn_Packets(Module, AutoCSR):
|
|||
# 0: Trigger packet
|
||||
self.symbol0 = CSR(9)
|
||||
self.sync += [
|
||||
upconn.tx_fifos.sink_stb[0].eq(self.symbol0.re),
|
||||
upconn.tx_fifos.sink_data[0].eq(self.symbol0.r[:8]),
|
||||
upconn.tx_fifos.sink_k[0].eq(self.symbol0.r[8]),
|
||||
upconn.tx_fifos.sink[0].stb.eq(self.symbol0.re),
|
||||
upconn.tx_fifos.sink[0].data.eq(self.symbol0.r[:8]),
|
||||
upconn.tx_fifos.sink[0].k.eq(self.symbol0.r[8]),
|
||||
]
|
||||
|
||||
|
||||
# 1: IO acknowledgment for trigger packet
|
||||
self.symbol1 = CSR(9)
|
||||
self.sync += [
|
||||
upconn.tx_fifos.sink_stb[1].eq(self.symbol1.re),
|
||||
upconn.tx_fifos.sink_data[1].eq(self.symbol1.r[:8]),
|
||||
upconn.tx_fifos.sink_k[1].eq(self.symbol1.r[8]),
|
||||
upconn.tx_fifos.sink[1].stb.eq(self.symbol1.re),
|
||||
upconn.tx_fifos.sink[1].data.eq(self.symbol1.r[:8]),
|
||||
upconn.tx_fifos.sink[1].k.eq(self.symbol1.r[8]),
|
||||
]
|
||||
|
||||
# 2: All other packets
|
||||
|
@ -70,9 +70,9 @@ class UpConn_Packets(Module, AutoCSR):
|
|||
|
||||
self.symbol2 = CSR(9)
|
||||
self.sync += [
|
||||
upconn.tx_fifos.sink_stb[2].eq(self.symbol2.re),
|
||||
upconn.tx_fifos.sink_data[2].eq(self.symbol2.r[:8]),
|
||||
upconn.tx_fifos.sink_k[2].eq(self.symbol2.r[8]),
|
||||
upconn.tx_fifos.sink[2].stb.eq(self.symbol2.re),
|
||||
upconn.tx_fifos.sink[2].data.eq(self.symbol2.r[:8]),
|
||||
upconn.tx_fifos.sink[2].k.eq(self.symbol2.r[8]),
|
||||
]
|
||||
|
||||
# TODO: put these stuff properly instead of declaring everytime
|
||||
|
|
Loading…
Reference in New Issue