forked from M-Labs/artiq-zynq
cxp: update txfifo sink port
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2346848541
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6d00f52638
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@ -48,18 +48,18 @@ class UpConn_Packets(Module, AutoCSR):
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# 0: Trigger packet
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# 0: Trigger packet
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self.symbol0 = CSR(9)
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self.symbol0 = CSR(9)
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self.sync += [
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self.sync += [
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upconn.tx_fifos.sink_stb[0].eq(self.symbol0.re),
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upconn.tx_fifos.sink[0].stb.eq(self.symbol0.re),
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upconn.tx_fifos.sink_data[0].eq(self.symbol0.r[:8]),
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upconn.tx_fifos.sink[0].data.eq(self.symbol0.r[:8]),
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upconn.tx_fifos.sink_k[0].eq(self.symbol0.r[8]),
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upconn.tx_fifos.sink[0].k.eq(self.symbol0.r[8]),
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]
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]
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# 1: IO acknowledgment for trigger packet
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# 1: IO acknowledgment for trigger packet
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self.symbol1 = CSR(9)
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self.symbol1 = CSR(9)
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self.sync += [
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self.sync += [
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upconn.tx_fifos.sink_stb[1].eq(self.symbol1.re),
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upconn.tx_fifos.sink[1].stb.eq(self.symbol1.re),
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upconn.tx_fifos.sink_data[1].eq(self.symbol1.r[:8]),
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upconn.tx_fifos.sink[1].data.eq(self.symbol1.r[:8]),
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upconn.tx_fifos.sink_k[1].eq(self.symbol1.r[8]),
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upconn.tx_fifos.sink[1].k.eq(self.symbol1.r[8]),
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]
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]
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# 2: All other packets
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# 2: All other packets
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@ -70,9 +70,9 @@ class UpConn_Packets(Module, AutoCSR):
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self.symbol2 = CSR(9)
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self.symbol2 = CSR(9)
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self.sync += [
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self.sync += [
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upconn.tx_fifos.sink_stb[2].eq(self.symbol2.re),
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upconn.tx_fifos.sink[2].stb.eq(self.symbol2.re),
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upconn.tx_fifos.sink_data[2].eq(self.symbol2.r[:8]),
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upconn.tx_fifos.sink[2].data.eq(self.symbol2.r[:8]),
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upconn.tx_fifos.sink_k[2].eq(self.symbol2.r[8]),
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upconn.tx_fifos.sink[2].k.eq(self.symbol2.r[8]),
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]
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]
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# TODO: put these stuff properly instead of declaring everytime
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# TODO: put these stuff properly instead of declaring everytime
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