diff --git a/src/libboard_artiq/src/cxp_downconn.rs b/src/libboard_artiq/src/cxp_downconn.rs
new file mode 100644
index 0000000..3c9dbf8
--- /dev/null
+++ b/src/libboard_artiq/src/cxp_downconn.rs
@@ -0,0 +1,71 @@
+use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
+use libboard_zynq::{println, timer::GlobalTimer};
+use log::info;
+
+use crate::pl::csr;
+
+pub fn main(timer: &mut GlobalTimer) {
+    unsafe {
+        info!("turning on pmc loopback mode...");
+        csr::cxp::loopback_mode_write(0b010); // Near-End PMA Loopback
+
+        // enable cxp gtx clock domains
+        csr::cxp::tx_start_init_write(1);
+        csr::cxp::rx_start_init_write(1);
+
+        info!("waiting for QPLL/CPLL to lock...");
+        timer.delay_us(50_000);
+        info!("tx_phaligndone = {} ", csr::cxp::txinit_phaligndone_read(),);
+
+        // enable txdata tranmission thought MGTXTXP, required by PMA loopback
+        csr::cxp::txenable_write(1);
+
+        loopback_testing(timer, 0x00, 0);
+    }
+
+    fn loopback_testing(timer: &mut GlobalTimer, data: u8, control_bit: u8) {
+        unsafe {
+            // send K28_5 for CDR to align
+            const K28_5: u8 = 0xBC;
+            csr::cxp::data_0_write(K28_5);
+            csr::cxp::control_bit_0_write(1);
+            csr::cxp::data_1_write(K28_5);
+            csr::cxp::control_bit_1_write(1);
+
+            info!("waiting for rx to align...");
+            while csr::cxp::rx_ready_read() != 1 {}
+            info!("rx ready!");
+
+            csr::cxp::data_1_write(data);
+            csr::cxp::control_bit_1_write(control_bit);
+            println!(
+                "data[0] = {:#04x} control bit = {:#b} encoded = {:#012b}",
+                csr::cxp::data_0_read(),
+                csr::cxp::control_bit_0_read(),
+                csr::cxp::encoded_0_read(),
+            );
+            println!(
+                "data[1] = {:#04x} control bit = {:#b} encoded = {:#012b}",
+                csr::cxp::data_1_read(),
+                csr::cxp::control_bit_1_read(),
+                csr::cxp::encoded_1_read(),
+            );
+
+            for _ in 0..20 {
+                timer.delay_us(100);
+                // println!(
+                //     "data[0] = {:#012b} data[1] = {:#012b}",
+                //     csr::cxp::rxdata_0_read(),
+                //     csr::cxp::rxdata_1_read(),
+                // );
+                println!(
+                    "decoded_data[0] = {:#04x} decoded_k[0] = {:#b} decoded_data[1] = {:#04x} decoded_k[1] = {:#b}",
+                    csr::cxp::decoded_data_0_read(),
+                    csr::cxp::decoded_k_0_read(),
+                    csr::cxp::decoded_data_1_read(),
+                    csr::cxp::decoded_k_1_read(),
+                );
+            }
+        }
+    }
+}
diff --git a/src/libboard_artiq/src/lib.rs b/src/libboard_artiq/src/lib.rs
index 008c2aa..3ffe429 100644
--- a/src/libboard_artiq/src/lib.rs
+++ b/src/libboard_artiq/src/lib.rs
@@ -42,8 +42,11 @@ pub mod si5324;
 pub mod si549;
 use core::{cmp, str};
 
+#[cfg(has_cxp)]
+pub mod cxp_downconn;
 #[cfg(has_cxp)]
 pub mod cxp_upconn;
+
 pub fn identifier_read(buf: &mut [u8]) -> &str {
     unsafe {
         pl::csr::identifier::address_write(0);