forked from M-Labs/artiq-zynq
cxp upconn gw: add low speed serial PHY
testing: add debug fifo output b4 encoder cxp upconn: add low speed serial cxp upconn: add reset, tx_busy, tx_enable cxp upconn: add clockgen module for 20.83Mbps & 41.66Mbps using counters cxp upconn: add oserdes using CEInserter cxp upconn: add packet scheduler with CEInserter scheduler: send priority packet during word/char boundary scheduler: send IDLE every 10000 words scheduler: encode packet before sending to oserdes
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@ -0,0 +1,374 @@
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from math import ceil
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from migen import *
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from migen.genlib.coding import PriorityEncoder
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from misoc.cores.code_8b10b import SingleEncoder
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from misoc.interconnect import stream
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from misoc.interconnect.csr import *
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from cxp_pipeline import upconn_layout
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IDLE_CHARS = Array([
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#[char, k]
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[0xBC, 1], #K28.5
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[0x3C, 1], #K28.1
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[0x3C, 1], #K28.1
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[0xB5, 0], #D21.5
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])
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@ResetInserter()
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class UpConn_ClockGen(Module):
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def __init__(self, sys_clk_freq):
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self.clk = Signal()
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self.clk_10x = Signal() # 20.83MHz 48ns or 41.66MHz 24ns
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self.freq2x_enable = Signal()
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# # #
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period = 1e9/sys_clk_freq
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max_count = ceil(48/period)
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counter = Signal(max=max_count, reset=max_count-1)
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clk_div = Signal(max=10, reset=9)
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self.sync += [
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self.clk.eq(0),
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self.clk_10x.eq(0),
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If(counter == 0,
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self.clk_10x.eq(1),
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If(self.freq2x_enable,
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counter.eq(int(max_count/2)-1),
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).Else(
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counter.eq(counter.reset),
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),
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).Else(
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counter.eq(counter-1),
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),
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If(counter == 0,
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If(clk_div == 0,
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self.clk.eq(1),
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clk_div.eq(clk_div.reset),
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).Else(
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clk_div.eq(clk_div-1),
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)
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)
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]
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@ResetInserter()
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@CEInserter()
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class SERDES_10bits(Module):
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def __init__(self, pad):
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self.oe = Signal()
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self.d = Signal(10)
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# # #
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o = Signal()
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tx_bitcount = Signal(max=10)
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tx_reg = Signal(10)
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# DEBUG:
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self.o = Signal()
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self.comb += self.o.eq(o)
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self.specials += Instance("OBUF", i_I=o, o_O=pad),
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self.sync += [
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If(self.oe,
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# send LSB first
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o.eq(tx_reg[0]),
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tx_reg.eq(Cat(tx_reg[1:], 0)),
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tx_bitcount.eq(tx_bitcount + 1),
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If(tx_bitcount == 9,
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tx_bitcount.eq(0),
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tx_reg.eq(self.d),
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),
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).Else(
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o.eq(0),
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tx_bitcount.eq(0),
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)
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]
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@ResetInserter()
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class Transmit_Scheduler(Module):
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def __init__(self, interface, debug_buf):
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self.tx_enable = Signal()
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self.oe = Signal()
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self.ce = Signal()
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# # #
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self.submodules.startup_fsm = startup_fsm = CEInserter()(FSM(reset_state="WAIT_TX_ENABLE"))
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self.submodules.encoder = encoder = CEInserter()(SingleEncoder(True))
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self.comb += [
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startup_fsm.ce.eq(self.ce),
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encoder.ce.eq(self.ce),
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]
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tx_charcount = Signal(max=4)
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tx_wordcount = Signal(max=10000)
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idling = Signal()
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priorities = Signal.like(interface.pe.o)
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# DEBUG:
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self.idling = Signal()
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self.tx_charcount = Signal(max=4)
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self.comb += [
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self.idling.eq(idling),
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self.tx_charcount.eq(tx_charcount),
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]
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startup_fsm.act("WAIT_TX_ENABLE",
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If(self.tx_enable,
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NextValue(idling, 1),
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NextValue(tx_charcount, 0),
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NextValue(encoder.d, IDLE_CHARS[0][0]),
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NextValue(encoder.k, IDLE_CHARS[0][1]),
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NextState("START_TX"),
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# DEBUG:
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If(debug_buf.sink_ack,
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NextValue(debug_buf.sink_stb, 1),
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NextValue(debug_buf.sink_data, IDLE_CHARS[0][0]),
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NextValue(debug_buf.sink_k, IDLE_CHARS[0][1]),
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)
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)
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)
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startup_fsm.act("START_TX",
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self.oe.eq(1),
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If((~self.tx_enable) & (tx_charcount == 3),
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NextState("WAIT_TX_ENABLE")
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)
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)
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# hold ack for only one sys clk cycle to prevent data loss
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for ack in interface.sink_ack:
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self.sync += ack.eq(0)
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self.sync += [
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debug_buf.sink_stb.eq(0),
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If(self.oe & self.ce,
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encoder.disp_in.eq(encoder.disp_out),
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If((~interface.pe.n) & (interface.pe.o == 0),
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# trigger packets are inserted at char boundary and don't contribute to word count
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interface.sink_ack[0].eq(1),
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encoder.d.eq(interface.sink_data[0]),
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encoder.k.eq(interface.sink_k[0]),
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# DEBUG:
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If(debug_buf.sink_ack,
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debug_buf.sink_stb.eq(1),
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debug_buf.sink_data.eq(interface.sink_data[0]),
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debug_buf.sink_k.eq(interface.sink_k[0]),
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)
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).Else(
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If(tx_charcount == 3,
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tx_charcount.eq(0),
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# Section 9.2.4 (CXP-001-2021)
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# other priorities packets are inserted at word boundary
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If((~interface.pe.n) & (tx_wordcount != 9999),
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idling.eq(0),
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priorities.eq(interface.pe.o),
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tx_wordcount.eq(tx_wordcount + 1),
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interface.sink_ack[interface.pe.o].eq(1),
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encoder.d.eq(interface.sink_data[interface.pe.o]),
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encoder.k.eq(interface.sink_k[interface.pe.o]),
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# DEBUG:
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If(debug_buf.sink_ack,
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debug_buf.sink_stb.eq(1),
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debug_buf.sink_data.eq(interface.sink_data[interface.pe.o]),
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debug_buf.sink_k.eq(interface.sink_k[interface.pe.o]),
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)
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).Else(
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# Section 9.2.5.1 (CXP-001-2021)
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# IDLE word shall be transmitted at least once every 10,000 words, but should not be inserted into trigger packet
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idling.eq(1),
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tx_wordcount.eq(0),
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encoder.d.eq(IDLE_CHARS[0][0]),
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encoder.k.eq(IDLE_CHARS[0][1]),
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# DEBUG:
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If(debug_buf.sink_ack,
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debug_buf.sink_stb.eq(1),
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debug_buf.sink_data.eq(IDLE_CHARS[0][0]),
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debug_buf.sink_k.eq(IDLE_CHARS[0][1]),
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)
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)
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).Else(
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tx_charcount.eq(tx_charcount + 1),
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If(~idling,
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tx_wordcount.eq(tx_wordcount + 1),
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interface.sink_ack[priorities].eq(1),
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encoder.d.eq(interface.sink_data[priorities]),
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encoder.k.eq(interface.sink_k[priorities]),
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# DEBUG:
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If(debug_buf.sink_ack,
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debug_buf.sink_stb.eq(1),
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debug_buf.sink_data.eq(interface.sink_data[priorities]),
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debug_buf.sink_k.eq(interface.sink_k[priorities]),
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)
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).Else(
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encoder.d.eq(IDLE_CHARS[tx_charcount + 1][0]),
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encoder.k.eq(IDLE_CHARS[tx_charcount + 1][1]),
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# DEBUG:
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If(debug_buf.sink_ack,
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debug_buf.sink_stb.eq(1),
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debug_buf.sink_data.eq(IDLE_CHARS[tx_charcount + 1][0]),
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debug_buf.sink_k.eq(IDLE_CHARS[tx_charcount + 1][1]),
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)
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)
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),
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),
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)
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]
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class PHY_Interface(Module):
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def __init__(self, layout, nsink):
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sink_stb = Signal(nsink)
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self.sink_ack = Array(Signal() for _ in range(nsink))
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self.sink_data = Array(Signal(8) for _ in range(nsink))
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self.sink_k = Array(Signal() for _ in range(nsink))
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# # #
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self.sinks = []
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for i in range(nsink):
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sink = stream.Endpoint(layout)
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self.sinks += [sink]
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self.comb += [
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sink.ack.eq(self.sink_ack[i]),
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sink_stb[i].eq(sink.stb),
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self.sink_data[i].eq(sink.data),
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self.sink_k[i].eq(sink.k),
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]
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# FIFOs transmission priority
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self.submodules.pe = PriorityEncoder(nsink)
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self.comb += self.pe.i.eq(sink_stb)
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class Debug_buffer(Module,AutoCSR):
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def __init__(self, layout):
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self.sink_stb = Signal()
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self.sink_ack = Signal()
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self.sink_data = Signal(8)
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self.sink_k = Signal()
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# # #
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self.submodules.buf_out = buf_out = stream.SyncFIFO(layout, 128)
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self.sync += [
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buf_out.sink.stb.eq(self.sink_stb),
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self.sink_ack.eq(buf_out.sink.ack),
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buf_out.sink.data.eq(self.sink_data),
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buf_out.sink.k.eq(self.sink_k),
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]
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self.inc = CSR()
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self.dout_pak = CSRStatus(8)
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self.kout_pak = CSRStatus()
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self.dout_valid = CSRStatus()
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self.sync += [
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# output
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buf_out.source.ack.eq(self.inc.re),
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self.dout_pak.status.eq(buf_out.source.data),
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self.kout_pak.status.eq(buf_out.source.k),
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self.dout_valid.status.eq(buf_out.source.stb),
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]
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class CXP_UpConn_PHY(Module, AutoCSR):
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def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads, nsink=3):
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self.bitrate2x_enable = Signal()
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self.clk_reset = Signal()
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self.tx_enable = Signal()
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self.tx_busy = Signal()
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# # #
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self.submodules.cg = cg = UpConn_ClockGen(sys_clk_freq)
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self.submodules.interface = interface = PHY_Interface(upconn_layout, nsink)
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self.sinks = interface.sinks
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# DEBUG:
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self.submodules.debug_buf = debug_buf = Debug_buffer(upconn_layout)
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self.submodules.scheduler = scheduler = Transmit_Scheduler(interface, debug_buf)
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self.submodules.serdes = serdes = SERDES_10bits(pad)
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self.comb += [
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self.tx_busy.eq(~interface.pe.n),
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cg.reset.eq(self.clk_reset),
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cg.freq2x_enable.eq(self.bitrate2x_enable),
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scheduler.reset.eq(self.clk_reset),
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scheduler.ce.eq(cg.clk),
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scheduler.tx_enable.eq(self.tx_enable),
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serdes.reset.eq(self.clk_reset),
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serdes.ce.eq(cg.clk_10x),
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serdes.d.eq(scheduler.encoder.output),
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serdes.oe.eq(scheduler.oe),
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]
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# DEBUG: remove pads
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prioity_0 = Signal()
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word_bound = Signal()
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p0 = Signal()
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p3 = Signal()
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self.comb += [
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prioity_0.eq((~interface.pe.n) & (interface.pe.o == 0)),
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word_bound.eq(scheduler.tx_charcount == 3),
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# because of clk delay
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p0.eq(scheduler.tx_charcount == 2),
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p3.eq(scheduler.tx_charcount == 1),
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]
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self.specials += [
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# # debug sma
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Instance("OBUF", i_I=serdes.o, o_O=debug_sma.p_tx),
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Instance("OBUF", i_I=cg.clk_10x, o_O=debug_sma.n_rx),
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# # pmod 0-7 pin
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# Instance("OBUF", i_I=serdes.o, o_O=pmod_pads[0]),
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# Instance("OBUF", i_I=cg.clk_10x, o_O=pmod_pads[1]),
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# Instance("OBUF", i_I=~tx_fifos.pe.n, o_O=pmod_pads[2]),
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# Instance("OBUF", i_I=prioity_0, o_O=pmod_pads[3]),
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# Instance("OBUF", i_I=word_bound, o_O=pmod_pads[4]),
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# Instance("OBUF", i_I=debug_buf.buf_out.sink.stb, o_O=pmod_pads[4]),
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# Instance("OBUF", i_I=debug_buf.buf_out.sink.ack, o_O=pmod_pads[5]),
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# Instance("OBUF", i_I=debug_buf.buf_out.source.stb, o_O=pmod_pads[6]),
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# Instance("OBUF", i_I=debug_buf.buf_out.source.ack, o_O=pmod_pads[7]),
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# Instance("OBUF", i_I=scheduler.idling, o_O=pmod_pads[5]),
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# # Instance("OBUF", i_I=tx_fifos.source_ack[0], o_O=pmod[6]),
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# # Instance("OBUF", i_I=tx_fifos.source_ack[2], o_O=pmod[6]),
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# # Instance("OBUF", i_I=tx_fifos.source_ack[1], o_O=pmod[7]),
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# Instance("OBUF", i_I=p0, o_O=pmod_pads[6]),
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# Instance("OBUF", i_I=p3, o_O=pmod_pads[7]),
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]
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