forked from M-Labs/artiq-zynq
pipeline GW: add busy csr
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5c253fefb6
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@ -283,6 +283,7 @@ class TX_Test_Packet(Module, AutoCSR):
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def __init__(self, layout):
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def __init__(self, layout):
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self.stb = CSR()
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self.stb = CSR()
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self.busy = CSRStatus()
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# # #
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# # #
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@ -292,7 +293,6 @@ class TX_Test_Packet(Module, AutoCSR):
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# Section 9.9.2 (CXP-001-2021)
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# Section 9.9.2 (CXP-001-2021)
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# 0x00, 0x01 ... 0xFF need to be send 16 times
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# 0x00, 0x01 ... 0xFF need to be send 16 times
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# cnt[8:12] is used to count up 16 times while cnt[:8] is the data
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# cnt[8:12] is used to count up 16 times while cnt[:8] is the data
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cnt = Signal(max=0x1000)
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cnt = Signal(max=0x1000)
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clr_cnt = Signal()
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clr_cnt = Signal()
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inc_cnt = Signal()
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inc_cnt = Signal()
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@ -337,3 +337,10 @@ class TX_Test_Packet(Module, AutoCSR):
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]
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]
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self.source = pak_wrp.source
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self.source = pak_wrp.source
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self.sync += \
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If(self.stb.re,
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self.busy.status.eq(1),
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).Elif(self.source.eop & self.source.ack,
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self.busy.status.eq(0)
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)
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