forked from M-Labs/artiq-zynq
cxp downconn firmware: packet testing
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94
src/libboard_artiq/src/cxp_downconn.rs
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94
src/libboard_artiq/src/cxp_downconn.rs
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use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
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use libboard_zynq::{println, timer::GlobalTimer};
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use log::info;
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use crate::{cxp_phys, cxp_proto, pl::csr::CXP};
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pub fn loopback_testing(channel: usize, timer: &mut GlobalTimer, speed: cxp_phys::CXP_SPEED) {
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println!("==============================================================================");
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cxp_phys::change_linerate(speed);
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unsafe {
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info!("waiting for tx&rx setup...");
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timer.delay_us(50_000);
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info!(
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"tx_phaligndone = {} | rx_phaligndone = {}",
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(CXP[channel].downconn_txinit_phaligndone_read)(),
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(CXP[channel].downconn_rxinit_phaligndone_read)(),
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);
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// enable txdata tranmission thought MGTXTXP, required by PMA loopback
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(CXP[channel].downconn_txenable_write)(1);
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info!("waiting for rx to align...");
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while (CXP[channel].downconn_rx_ready_read)() != 1 {}
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info!("rx ready!");
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cxp_proto::downconn_send_test_packet(channel);
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// FIXME: why test + trig ack doesn't work well for rx??
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cxp_proto::downconn_debug_send_trig_ack(channel);
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const DATA_MAXSIZE: usize = 253;
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let data_size = 4; // no. of bytes
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let data: u32 = 0xDADA as u32;
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let mut data_slice: [u8; DATA_MAXSIZE] = [0; DATA_MAXSIZE];
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data_slice[..4].clone_from_slice(&data.to_be_bytes());
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cxp_proto::downconn_debug_send(
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channel,
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&cxp_proto::UpConnPacket::Event {
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conn_id: 0x1234_5678_u32,
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packet_tag: 0x69_u8,
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length: data_size + 3,
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event_size: data_size,
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namespace: 0x02_u8,
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event_id: 0x00_6969u16,
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timestamp: 0x1234_5678u64,
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data: data_slice,
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},
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)
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.expect("loopback gtx tx error");
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timer.delay_us(1000); // wait packet has arrive at RX async fifo
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if (CXP[channel].downconn_trigger_ack_read)() == 1 {
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(CXP[channel].downconn_trigger_ack_write)(1);
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info!("trig ack and cleared");
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}
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if (CXP[channel].downconn_bootstrap_decoder_err_read)() == 1 {
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info!("!!!!!!!DECODER ERROR!!!!!!! and cleared");
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(CXP[channel].downconn_bootstrap_decoder_err_write)(1);
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}
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if (CXP[channel].downconn_bootstrap_test_err_read)() == 1 {
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info!("!!!!!!!TEST ERROR!!!!!!! and cleared");
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(CXP[channel].downconn_bootstrap_test_err_write)(1);
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}
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info!("packet type = {:#06X}", (CXP[channel].downconn_packet_type_read)());
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cxp_proto::receive(channel).expect("loopback gtx rx error");
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// cxp_proto::downconn_debug_mem_print(channel);
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// DEBUG: print loopback packets
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const LEN: usize = 20;
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let mut pak_arr: [u32; LEN] = [0; LEN];
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let mut k_arr: [u8; LEN] = [0; LEN];
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let mut i: usize = 0;
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while (CXP[channel].downconn_debug_out_dout_valid_read)() == 1 {
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pak_arr[i] = (CXP[channel].downconn_debug_out_dout_pak_read)();
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k_arr[i] = (CXP[channel].downconn_debug_out_kout_pak_read)();
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// println!("received {:#04X}", pak_arr[i]);
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(CXP[channel].downconn_debug_out_inc_write)(1);
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i += 1;
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if i == LEN {
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break;
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}
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}
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info!("rx ready = {}", (CXP[channel].downconn_rx_ready_read)());
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// cxp_proto::print_packetu32(&pak_arr, &k_arr);
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}
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}
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