forked from M-Labs/artiq-zynq
cxp downconn: cleanup debug csr
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7e6d4e186f
commit
679b430d74
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@ -12,6 +12,7 @@ from operator import add
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class CXP_DownConn(Module, AutoCSR):
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def __init__(self, refclk, pads, sys_clk_freq, debug_sma, pmod_pads):
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nconn = len(pads)
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self.rx_start_init = CSRStorage()
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self.rx_restart = CSR()
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@ -19,9 +20,7 @@ class CXP_DownConn(Module, AutoCSR):
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self.tx_restart = CSR()
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self.txenable = CSRStorage()
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self.txinit_phaligndone = CSRStatus()
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self.rxinit_phaligndone = CSRStatus()
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self.rx_ready = CSRStatus()
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self.rx_ready = CSRStatus(nconn)
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self.qpll_reset = CSR()
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self.qpll_locked = CSRStatus()
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@ -36,7 +35,6 @@ class CXP_DownConn(Module, AutoCSR):
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]
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nconn = len(pads)
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for i in range(nconn):
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if i != 0:
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@ -65,9 +63,6 @@ class CXP_DownConn(Module, AutoCSR):
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for gtx in self.gtxs:
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self.sync += [
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self.txinit_phaligndone.status.eq(gtx.tx_init.Xxphaligndone),
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self.rxinit_phaligndone.status.eq(gtx.rx_init.Xxphaligndone),
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self.rx_ready.status.eq(gtx.rx_ready),
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gtx.txenable.eq(self.txenable.storage[0]),
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gtx.tx_restart.eq(self.tx_restart.re),
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@ -78,7 +73,6 @@ class CXP_DownConn(Module, AutoCSR):
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self.comb += gtx.dclk.eq(ClockSignal("sys"))
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self.sync += [
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gtx.den.eq(0),
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gtx.dwen.eq(0),
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If(self.gtx_dread.re,
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@ -90,6 +84,12 @@ class CXP_DownConn(Module, AutoCSR):
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gtx.daddr.eq(self.gtx_daddr.storage),
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gtx.din.eq(self.gtx_din.storage),
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),
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]
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# TODO: deal with 4 GTX instance of outpus
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for n, gtx in enumerate(self.gtxs):
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self.sync += [
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self.rx_ready.status[n].eq(gtx.rx_ready),
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If(gtx.dready,
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self.gtx_dready.w.eq(1),
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self.gtx_dout.status.eq(gtx.dout),
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@ -115,6 +115,9 @@ class CXP_DownConn(Module, AutoCSR):
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self.pll_dout = CSRStatus(16)
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self.pll_dready = CSRStatus()
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self.txinit_phaligndone = CSRStatus()
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self.rxinit_phaligndone = CSRStatus()
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for n, gtx in enumerate(self.gtxs):
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self.comb += [
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gtx.txpll_reset.eq(self.txpll_reset.storage),
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@ -124,7 +127,8 @@ class CXP_DownConn(Module, AutoCSR):
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gtx.pll_din.eq(self.pll_din.storage),
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gtx.pll_dwen.eq(self.pll_dwen.storage),
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self.txpll_locked.status.eq(gtx.txpll_locked),
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self.txinit_phaligndone.status.eq(gtx.tx_init.Xxphaligndone),
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self.rxinit_phaligndone.status.eq(gtx.rx_init.Xxphaligndone), self.txpll_locked.status.eq(gtx.txpll_locked),
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self.pll_dout.status.eq(gtx.pll_dout),
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self.pll_dready.status.eq(gtx.pll_dready),
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]
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@ -169,38 +173,29 @@ class CXP_DownConn(Module, AutoCSR):
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gtx.encoder.k[3].eq(0),
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]
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self.rxdata_0 = CSRStatus(10)
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self.rxdata_1 = CSRStatus(10)
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self.rxdata_2 = CSRStatus(10)
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self.rxdata_3 = CSRStatus(10)
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self.decoded_data_0 = CSRStatus(8)
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self.decoded_data_1 = CSRStatus(8)
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self.decoded_data_2 = CSRStatus(8)
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self.decoded_data_3 = CSRStatus(8)
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self.decoded_k_0 = CSRStatus()
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self.decoded_k_1 = CSRStatus()
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self.decoded_k_2 = CSRStatus()
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self.decoded_k_3 = CSRStatus()
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for i in range(4):
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gtx.decoders[i].input.attr.add("no_retiming")
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gtx.decoders[i].d.attr.add("no_retiming")
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gtx.decoders[i].k.attr.add("no_retiming")
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rxdata_name = "rxdata_" + str(i)
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rxdata_csr = CSRStatus(10, name=rxdata_name)
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setattr(self, rxdata_name, rxdata_csr)
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decoded_name = "decoded_data_" + str(i)
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decoded_csr = CSRStatus(8, name=decoded_name)
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setattr(self, decoded_name, decoded_csr)
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k_name = "rxdata_" + str(i)
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k_csr = CSRStatus(1, name=k_name)
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setattr(self, k_name, k_csr)
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self.sync.cxp_gtx_rx += [
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self.rxdata_0.status.eq(gtx.decoders[0].input),
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self.decoded_data_0.status.eq(gtx.decoders[0].d),
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self.decoded_k_0.status.eq(gtx.decoders[0].k),
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self.rxdata_1.status.eq(gtx.decoders[1].input),
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self.decoded_data_1.status.eq(gtx.decoders[1].d),
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self.decoded_k_1.status.eq(gtx.decoders[1].k),
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self.rxdata_2.status.eq(gtx.decoders[2].input),
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self.decoded_data_2.status.eq(gtx.decoders[2].d),
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self.decoded_k_2.status.eq(gtx.decoders[2].k),
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self.rxdata_3.status.eq(gtx.decoders[3].input),
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self.decoded_data_3.status.eq(gtx.decoders[3].d),
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self.decoded_k_3.status.eq(gtx.decoders[3].k),
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rxdata_csr.status.eq(gtx.decoders[i].input),
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decoded_csr.status.eq(gtx.decoders[i].d),
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k_csr.status.eq(gtx.decoders[i].k),
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]
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class QPLL(Module, AutoCSR):
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def __init__(self, refclk, sys_clk_freq):
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self.clk = Signal()
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@ -392,8 +387,6 @@ class Comma_Checker(Module):
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rxfsm.act("WAIT_COMMA",
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If(self.comma_det,
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# # start aligner early, so word aligned will fall
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# self.aligner_en_rxclk.eq(1),
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NextState("ALIGNING"),
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)
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)
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