forked from M-Labs/artiq-zynq
cxp downconn: update to accept a list of gtx pins
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3102dd8a52
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@ -30,8 +30,10 @@ class CXP_DownConn(Module, AutoCSR):
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self.submodules.qpll = qpll = QPLL(refclk, sys_clk_freq)
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self.submodules.qpll = qpll = QPLL(refclk, sys_clk_freq)
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# TODO: add gtx slave channel
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# single & master tx_mode can lock with rx in loopback
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# single & master tx_mode can lock with rx in loopback
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self.submodules.gtx = gtx = GTX(self.qpll, pads, sys_clk_freq, tx_mode="single", rx_mode="single")
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self.submodules.gtx = gtx = GTX(self.qpll, pads[0], sys_clk_freq, tx_mode="single", rx_mode="single")
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# NOTE: No need to connect cxp_gtx_tx, we don't use tx anyway (just for loopback)
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# NOTE: No need to connect cxp_gtx_tx, we don't use tx anyway (just for loopback)
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