forked from M-Labs/artiq-zynq
cxp upconn: refactor serial fsm as sync logic
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bd66659883
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6636339701
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@ -58,38 +58,9 @@ class CXP_UpConn(Module, AutoCSR):
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o = Signal()
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o = Signal()
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bits = Signal(max=tx_width)
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bits = Signal(max=tx_width)
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tx_reg = Signal(tx_width)
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tx_reg = Signal(tx_width)
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busy = Signal()
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self.submodules.fsm = ClockDomainsRenamer("cxp_upconn")(FSM(reset_state="IDLE"))
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self.submodules.encoder = SingleEncoder(True)
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self.submodules.encoder = SingleEncoder(True)
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self.fsm.act("IDLE",
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NextValue(o, 0),
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If(self.stb.storage,
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NextValue(bits, 0),
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NextValue(tx_reg, self.encoder.output),
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NextValue(self.tx_reg.status, self.encoder.output),
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NextValue(self.encoder.disp_in, self.encoder.disp_out),
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NextState("WRITE")
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)
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)
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self.fsm.act("WRITE",
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NextValue(o, tx_reg[0]),
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NextValue(tx_reg, Cat(tx_reg[1:], 0)),
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If(bits == tx_width - 1,
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If(self.stb.storage,
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NextValue(bits, 0),
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NextValue(tx_reg, self.encoder.output),
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NextValue(self.tx_reg.status, self.encoder.output),
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NextValue(self.encoder.disp_in, self.encoder.disp_out),
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).Else(
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NextState("IDLE"),
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),
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).Else(
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NextValue(bits, bits + 1)
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)
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)
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self.comb += [
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self.comb += [
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self.encoder.d.eq(self.data.storage),
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self.encoder.d.eq(self.data.storage),
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self.encoder.k.eq(self.k_symbol.storage),
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self.encoder.k.eq(self.k_symbol.storage),
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@ -97,9 +68,20 @@ class CXP_UpConn(Module, AutoCSR):
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self.sync.cxp_upconn +=[
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self.sync.cxp_upconn +=[
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self.encoded.status.eq(self.encoder.output),
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self.encoded.status.eq(self.encoder.output),
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If(self.stb.storage,
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o.eq(tx_reg[0]),
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tx_reg.eq(Cat(tx_reg[1:], 0))
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),
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If(bits != tx_width - 1,
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bits.eq(bits + 1),
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).Elif(self.stb.storage,
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bits.eq(0),
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tx_reg.eq(self.encoder.output),
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self.tx_reg.status.eq(self.encoder.output),
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self.encoder.disp_in.eq(self.encoder.disp_out),
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)
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]
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]
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self.comb += busy.eq(~self.fsm.ongoing("IDLE"))
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# DEBUG: remove pads
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# DEBUG: remove pads
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self.specials += [
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self.specials += [
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Instance("OBUF", i_I=o, o_O=pads.p_tx),
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Instance("OBUF", i_I=o, o_O=pads.p_tx),
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