forked from M-Labs/artiq-zynq
cxp upconn: refactor idle into its submodule
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dbf7ac1cb9
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6134ad5794
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@ -6,15 +6,6 @@ from misoc.cores.code_8b10b import SingleEncoder
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from misoc.interconnect import stream
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from misoc.interconnect.csr import *
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# CXP 2.1 section 9.2.5
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IDLE_CHARS = [
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#[data, k]
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[0b10111100, 1], #K28.5
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[0b00111100, 1], #K28.1
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[0b00111100, 1], #K28.1
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[0b10111100, 0], #D28.5
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]
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class CXP_UpConn(Module, AutoCSR):
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def __init__(self, pads, sys_clk_freq, pmod, nfifos=3, fifo_depth=32):
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@ -59,8 +50,8 @@ class CXP_UpConn(Module, AutoCSR):
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]
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self.submodules.fsm = ClockDomainsRenamer("cxp_upconn")(FSM(reset_state="WAIT_TX_ENABLE"))
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self.submodules.encoder = ClockDomainsRenamer("cxp_upconn")(SingleEncoder(True))
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self.submodules.tx_fifos = TxFIFOs(nfifos, fifo_depth)
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self.submodules.tx_idle = TxIdle()
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o = Signal()
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tx_en = Signal()
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@ -75,11 +66,11 @@ class CXP_UpConn(Module, AutoCSR):
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# startup sequence
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self.fsm.act("WAIT_TX_ENABLE",
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NextValue(self.tx_idle.disp_in, 0),
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NextValue(self.tx_idle.word_idx, 0),
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If(self.tx_enable.storage,
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NextValue(self.encoder.d, IDLE_CHARS[0][0]),
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NextValue(self.encoder.k, IDLE_CHARS[0][1]),
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NextValue(self.encoder.disp_in, 0),
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NextValue(tx_wordcount, 1),
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NextValue(tx_wordcount, 0),
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NextValue(tx_bitcount, 0),
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NextState("LOAD_CHAR")
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)
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@ -87,44 +78,33 @@ class CXP_UpConn(Module, AutoCSR):
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self.fsm.act("LOAD_CHAR",
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NextValue(idling, 1),
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NextValue(tx_reg, self.encoder.output),
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NextValue(disp, self.encoder.disp_out),
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NextValue(self.tx_idle.source_ack, 1),
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NextValue(tx_reg, self.tx_idle.source_data),
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NextValue(disp, self.tx_idle.disp_out),
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NextState("START_TX")
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)
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self.fsm.act("START_TX",
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tx_en.eq(1),
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If((~self.tx_enable.storage) & (tx_bitcount == 9),
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If((~self.tx_enable.storage) & (tx_wordcount == 3),
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NextState("WAIT_TX_ENABLE")
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)
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)
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idle_ack = Signal()
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# CXP 2.1 section 9.2.4
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# Higher priority packet can be inserted into a lower priority packet during transmission
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# Priority lv 0 can be inserted in char boundary of the packet
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# Priority lv 1-2 need to be inserted in word boundary of the packet
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self.sync.cxp_upconn += [
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self.tx_fifos.disp_in.eq(disp),
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self.tx_idle.disp_in.eq(disp),
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If(tx_en,
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o.eq(tx_reg[0]),
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tx_reg.eq(Cat(tx_reg[1:], 0)),
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tx_bitcount.eq(tx_bitcount + 1),
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self.tx_fifos.disp_in.eq(disp),
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self.encoder.disp_in.eq(disp),
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If(idle_ack,
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# reset after asserted
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idle_ack.eq(0),
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If(tx_wordcount == 3,
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self.encoder.d.eq(Array(IDLE_CHARS)[0][0]),
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self.encoder.k.eq(Array(IDLE_CHARS)[0][1]),
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).Else(
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self.encoder.d.eq(Array(IDLE_CHARS)[tx_wordcount + 1][0]),
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self.encoder.k.eq(Array(IDLE_CHARS)[tx_wordcount + 1][1]),
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)
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),
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# char boundary
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If(tx_bitcount == 9,
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@ -154,9 +134,9 @@ class CXP_UpConn(Module, AutoCSR):
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).Else(
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idling.eq(1),
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idle_ack.eq(1),
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tx_reg.eq(self.encoder.output),
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disp.eq(self.encoder.disp_out),
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self.tx_idle.source_ack.eq(1),
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tx_reg.eq(self.tx_idle.source_data),
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disp.eq(self.tx_idle.disp_out),
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)
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).Else(
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If(~idling,
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@ -164,9 +144,9 @@ class CXP_UpConn(Module, AutoCSR):
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tx_reg.eq(self.tx_fifos.source_data[priority]),
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disp.eq(self.tx_fifos.disp_out[priority]),
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).Else(
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idle_ack.eq(1),
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tx_reg.eq(self.encoder.output),
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disp.eq(self.encoder.disp_out),
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self.tx_idle.source_ack.eq(1),
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tx_reg.eq(self.tx_idle.source_data),
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disp.eq(self.tx_idle.disp_out),
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)
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),
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)
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@ -176,7 +156,6 @@ class CXP_UpConn(Module, AutoCSR):
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)
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]
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# DEBUG: remove pads
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assert len(IDLE_CHARS) == 4 #word length must be 4 chars
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self.encoded_data = CSRStatus(10)
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self.sync.cxp_upconn +=[
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If(tx_bitcount == 0,
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@ -187,13 +166,13 @@ class CXP_UpConn(Module, AutoCSR):
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ninth_bit = Signal()
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word_bound = Signal()
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p1 = Signal()
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p2 = Signal()
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p0 = Signal()
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p3 = Signal()
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self.comb += [
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ninth_bit.eq(tx_bitcount == 9),
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word_bound.eq(tx_wordcount == 3),
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p1.eq(priority == 1),
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p2.eq(priority == 2),
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p0.eq(self.tx_idle.word_idx == 0),
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p3.eq(self.tx_idle.word_idx == 3),
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]
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self.specials += [
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# debug sma
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@ -210,8 +189,8 @@ class CXP_UpConn(Module, AutoCSR):
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# Instance("OBUF", i_I=self.tx_fifos.source_ack[0], o_O=pmod[6]),
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# Instance("OBUF", i_I=self.tx_fifos.source_ack[2], o_O=pmod[6]),
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# Instance("OBUF", i_I=self.tx_fifos.source_ack[1], o_O=pmod[7]),
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Instance("OBUF", i_I=p1, o_O=pmod[6]),
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Instance("OBUF", i_I=p2, o_O=pmod[7]),
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Instance("OBUF", i_I=p0, o_O=pmod[6]),
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Instance("OBUF", i_I=p3, o_O=pmod[7]),
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]
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self.symbol0 = CSR(9)
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self.symbol1 = CSR(9)
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@ -226,7 +205,7 @@ class CXP_UpConn(Module, AutoCSR):
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self.tx_fifos.sink_data[2].eq(self.symbol2.r),
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]
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class TxFIFOs(Module, AutoCSR):
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class TxFIFOs(Module):
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def __init__(self, nfifos, fifo_depth):
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self.disp_in = Signal()
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self.disp_out = Array(Signal() for _ in range(nfifos))
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@ -235,13 +214,13 @@ class TxFIFOs(Module, AutoCSR):
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self.sink_ack = Signal(nfifos)
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self.sink_data = [Signal(9) for _ in range(nfifos)]
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# data & ack will be used dynamically during runtime, cannot use python array
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self.source_stb = Signal(nfifos)
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self.source_ack = Array(Signal() for _ in range(nfifos))
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self.source_data = Array(Signal(10) for _ in range(nfifos))
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# # #
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source_stb = Signal(nfifos)
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for i in range(nfifos):
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cdr = ClockDomainsRenamer({"write": "sys", "read": "cxp_upconn"})
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fifo = cdr(stream.AsyncFIFO([("data", 9)], fifo_depth))
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@ -259,13 +238,54 @@ class TxFIFOs(Module, AutoCSR):
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encoder.disp_in.eq(self.disp_in),
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self.disp_out[i].eq(encoder.disp_out),
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self.source_stb[i].eq(fifo.source.stb),
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source_stb[i].eq(fifo.source.stb),
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fifo.source.ack.eq(self.source_ack[i]),
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self.source_data[i].eq(encoder.output),
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# reset ack after asserted
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If(self.source_ack[i], self.source_ack[i].eq(0)),
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]
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# For FIFOs transmission priority
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# FIFOs transmission priority
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self.submodules.pe = PriorityEncoder(nfifos)
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self.comb += self.pe.i.eq(self.source_stb)
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self.comb += self.pe.i.eq(source_stb)
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class TxIdle(Module):
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def __init__(self):
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self.disp_in = Signal()
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self.disp_out = Signal()
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self.word_idx = Signal(max=4)
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self.source_ack = Signal()
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self.source_data = Signal(10)
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# # #
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# CXP 2.1 section 9.2.5
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IDLE_CHARS = Array([
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#[data, k]
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[0b10111100, 1], #K28.5
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[0b00111100, 1], #K28.1
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[0b00111100, 1], #K28.1
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[0b10111100, 0], #D28.5
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])
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encoder = ClockDomainsRenamer("cxp_upconn")(SingleEncoder(True))
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self.submodules += encoder
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self.sync.cxp_upconn += [
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encoder.d.eq(IDLE_CHARS[self.word_idx][0]),
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encoder.k.eq(IDLE_CHARS[self.word_idx][1]),
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encoder.disp_in.eq(self.disp_in),
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self.disp_out.eq(encoder.disp_out),
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self.source_data.eq(encoder.output),
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If(self.source_ack,
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# reset after asserted
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self.source_ack.eq(0),
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If(self.word_idx != 3,
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self.word_idx.eq(self.word_idx + 1),
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).Else(
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self.word_idx.eq(0),
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)
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),
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]
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